There are two limitations on the power handling ability of
a transistor: average junction temperature and second
breakdown. Safe operating area curves indicate I
C
− V
CE
limits of the transistor that must be observed for reliable
operation: i.e., the transistor must not be subjected to greater
dissipation than the curves indicate.
The data of Figure 2 is based on T
J(pk)
= 200_C; T
C
is
variable depending on conditions. Second breakdown pulse
limits are valid for duty cycles to 10% provided T
J(pk)
v
200_C. T
J(pk)
may be calculated from the data in
Figure 13. At high case temperatures, thermal limitations
will reduce the power that can be handled to values less than
the limitations imposed by second breakdown.
Figure 2. Maximum Rated Forward Biased
Safe Operating Area
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2
MJ14001 (PNP), MJ14002* (NPN), MJ14003* (PNP)
TYPICAL ELECTRICAL CHARACTERISTICS
MJ14002 (NPN)
300
200
hFE , DC CURRENT GAIN
hFE , DC CURRENT GAIN
100
70
50
30
20
10
7.0
5.0
3.0
0.7 1.0
2.0 3.0
5.0 7.0 10
20 30
I
C
, COLLECTOR CURRENT (AMPS)
50
70
V
CE
= 3.0 V
T
J
= −55°C
T
J
= 25°C
T
J
= 150°C
300
200
100
70
50
30
20
10
7.0
5.0
3.0
0.7 1.0
2.0 3.0
5.0 7.0 10
20
I
C
, COLLECTOR CURRENT (AMPS)
30
50
70
V
CE
= 3.0 V
T
J
= −55°C
T
J
= 25°C
T
J
= 150°C
MJ14001, MJ14003 (PNP)
Figure 3. DC Current Gain
VCE , COLLECTOR−EMITTER VOLTAGE (VOLTS)
VCE , COLLECTOR−EMITTER VOLTAGE (VOLTS)
2.8
2.4
2.0
1.6
I
C
= 25 A
1.2
0.8
0.4
0
0.1
0.2 0.3
0.5 0.7 1.0
2.0
3.0
5.0 7.0 10
I
C
= 10 A
T
J
= 25°C
2.8
2.4
2.0
1.6
Figure 4. DC Current Gain
I
C
= 60 A
T
J
= 25°C
I
C
= 60 A
I
C
= 25 A
1.2
0.8
0.4
0
0.1
0.2
0.3
0.5 0.7 1.0
2.0 3.0
I
B
, BASE CURRENT (AMPS)
5.0 7.0
10
I
C
= 10 A
I
B
, BASE CURRENT (AMPS)
Figure 5. Collector Saturation Region
2.8
2.4
V, VOLTAGE (VOLTS)
2.0
1.6
1.2
0.8
0.4
0
0.7
1.0
V
BE(sat)
@ I
C
/I
B
= 10
V
BE(on)
@ V
CE
= 3.0 V
V
CE(sat)
@ I
C
/I
B
= 10
2.0
5.0 7.0 10
20 30
3.0
I
C
, COLLECTOR CURRENT (AMPS)
50
70
0.4
0
0.7
1.0
T
J
= 25°C
V, VOLTAGE (VOLTS)
2.8
2.4
2.0
1.6
1.2
0.8
Figure 6. Collector Saturation Region
T
J
= 25°C
V
BE(sat)
@ I
C
/I
B
= 10
V
BE(on)
@ V
CE
= 3.0 V
V
CE(sat)
@ I
C
/I
B
= 10
2.0 3.0
5.0 7.0 10
20 30
I
C
, COLLECTOR CURRENT (AMPS)
50
70
Figure 7. “On” Voltages
Figure 8. “On” Voltages
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3
MJ14001 (PNP), MJ14002* (NPN), MJ14003* (PNP)
1.0
0.7
0.5
0.3
t, TIME (
μ
s)
0.2
0.1
0.07
0.05
0.03
0.02
0.01
0.7 1.0
MJ14002 (NPN)
MJ14001, MJ14003 (PNP)
2.0 3.0
5.0 7.0 10
20 30
I
C
, COLLECTOR CURRENT (AMPS)
50
70
t
d
t
r
t, TIME (
μ
s)
1.0
0.7
0.5
0.3
0.2
0.1
0.07
0.04
0.7 1.0
t
f
4.0
3.0
2.0
t
s
MJ14002 (NPN)
MJ14001, MJ14003 (PNP)
2.0 3.0
5.0 7.0 10
20 30
I
C
, COLLECTOR CURRENT (AMPS)
50
70
Figure 9. Turn−On Switching Times
Figure 10. Turn−Off Switching Times
V
CC
+2.0 V
0
10000
7000
5000
C, CAPACITANCE (pF)
3000
2000
1000
700
500
300
200
100
1.0
C
ib
C
ob
T
J
= 25°C
MJ14002 (NPN)
MJ14001, MJ14003 (PNP)
2.0
3.0
5.0 7.0 10
20 30
V
R
, REVERSE VOLTAGE (VOLTS)
50
70 100
C
ib
C
ob
0
−12 V
t
r
≤
20 ns
−12 V
R
L
R
B
−30 V
TO SCOPE
t
r
≤
20 ns
10 to 100
ms
DUTY CYCLE
≈
2.0%
+10
V
V
CC
R
L
−30 V
R
B
TO SCOPE
t
r
≤
20 ns
t
r
≤
20 ns
10 to 100
ms
V
BB
DUTY CYCLE
≈
2.0%
+7.0 V
FOR CURVES OF FIGURES 3 & 6, R
B
& R
L
ARE VARIED.
INPUT LEVELS ARE APPROXIMATELY AS SHOWN.
FOR NPN CIRCUITS, REVERSE ALL POLARITIES.
Figure 11. Capacitance Variation
r(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED)
Figure 12. Switching Test Circuit
1.0
0.7
0.5
0.3
0.2
0.1
0.07
0.05
0.03
0.02
D = 0.5
0.2
0.1
0.05
0.02
0.01
SINGLE PULSE
0.05
0.07
0.1
0.2 0.3
0.5 0.7 1.0
2.0 3.0 5.0 7.0 10
t, TIME (ms)
20 30
50 70 100
200 300
500 700 1000 2000
R
qJC(t)
= r(t) R
qJC
R
qJC
= 0.584°C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
1
T
J(pk)
− T
C
= P
(pk)
R
qJC(t)
P
(pk)
t
1
t
2
DUTY CYCLE, D = t
1
/t
2
0.01
0.02 0.03
Figure 13. Thermal Response
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4
MJ14001 (PNP), MJ14002* (NPN), MJ14003* (PNP)
PACKAGE DIMENSIONS
TO−204 (TO−3)
CASE 197A−05
ISSUE K
A
N
C
−T−
E
D
2 PL
SEATING
PLANE
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
INCHES
MIN
MAX
1.530 REF
0.990 1.050
0.250 0.335
0.057 0.063
0.060 0.070
0.430 BSC
0.215 BSC
0.440 0.480
0.665 BSC
0.760 0.830
0.151 0.165
1.187 BSC
0.131 0.188
MILLIMETERS
MIN MAX
38.86 REF
25.15 26.67
6.35
8.51
1.45
1.60
1.53
1.77
10.92 BSC
5.46 BSC
11.18 12.19
16.89 BSC
19.31 21.08
3.84
4.19
30.15 BSC
3.33
4.77
K
M
0.30 (0.012)
T Q
M
Y
M
U
V
2
L
G
−Y−
H
B
DIM
A
B
C
D
E
G
H
K
L
N
Q
U
V
1
−Q−
0.25 (0.010)
M
STYLE 1:
PIN 1. BASE
2. EMITTER
CASE: COLLECTOR
T Y
M
ON Semiconductor
and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
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operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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