EX64-TQG64 datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Programmable logic devices> Programmable logic> EX64-TQG64

EX64-TQG64: DescriptionFPGA - Field Programmable Gate Array eX; CategoryProgrammable logic devices Programmable logic; File Size3MB，52 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com; Environmental Compliance

Download Datasheet Parametric View All

EX64-TQG64 Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	EX64-TQG64	-	-	View	Buy Now

EX64-TQG64 Overview

FPGA - Field Programmable Gate Array eX

EX64-TQG64 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Microsemi
package instruction	LFQFP,
Reach Compliance Code	compliant
Is Samacsys	N
Other features	LG-MIN; WD-MIN; TERM PITCH-MIN
maximum clock frequency	250 MHz
Combined latency of CLB-Max	1 ns
JESD-30 code	S-PQFP-G64
JESD-609 code	e3
length	10 mm
Humidity sensitivity level	3
Equivalent number of gates	3000
Number of terminals	64
Maximum operating temperature	70 °C
Minimum operating temperature
organize	3000 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Maximum seat height	1.6 mm
Maximum supply voltage	2.7 V
Minimum supply voltage	2.3 V
Nominal supply voltage	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Matte Tin (Sn)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	40
width	10 mm
Base Number Matches	1

Preview

Download Datasheet

View All

Revision 5

ex Automotive Family FPGAs

Specifications

•

3,000 to 12,000 Available System Gates

Maximum 512 Flip-Flops (Using CC Macros)

0.22

μm

CMOS Process Technology

Up to 132 User-Programmable I/O Pins

•

Live on Power-Up

No Power-Up/Down Sequence Required for Supply

Voltages

Configurable Weak Resistor Pull-Up or Pull-Down for

Tristated Outputs during Power-Up

Individual Output Slew-Rate Control

2.5 V and 3.3 V I/Os

Software Design Support with Designer and Libero

Integrated Design Environment (IDE) Tools

Up to 100% Resource Utilization with 100% Pin Locking

Deterministic Timing

Unique In-System Diagnostic and Verification Capability

with Silicon Explorer II

Boundary Scan Testing in Compliance with IEEE

Standard 1149.1 (JTAG)

FuseLock™ Secure Programming Technology Designed

to Prevent Reverse Engineering and Design Theft

Features

•

250 MHz Internal Performance, Low-Power Antifuse

FPGA

Advanced Small-Footprint Packages

Pin-to-Pin Compatibility with eX Commercial- and

Industrial-Grade Devices

Hot-Swap Compliant I/Os

Single-Chip Solution

Nonvolatile

Product Profile

Device

Capacity

System Gates

Typical Gates

Dedicated Flip-Flops

Maximum Flip-Flops

Combinatorial Cells

Maximum User I/Os

Global Clocks

Hardwired

Routed

Speed Grades*

Temperature Grades*

Package

(by pin count)

3,000

2,000

6,000

4,000

12,000

8,000

eX64

eX128

eX256

128

Std.

64, 100

49, 128

128

256

100

Std.

64, 100

49, 128

256

512

132

Std.

100

128, 180

Note:

* The eX family is also offered in commercial and industrial temperature grades with –F, –P, and Std. speed grades. Refer to

the

eX Family FPGAs

datasheet for more details.

October 2012

ex Automotive Family FPGAs

Table of Contents

ex Automotive Family FPGAs

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

eX Family Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14

Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15

2.5 V LVCMOS2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16

3.3 V LVTTL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17

CEQ Values for eX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19

Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19

eX Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20

Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24

Temperature and Voltage Derating Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24

eX Family Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28

Package Pin Assignments

TQ64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

TQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

CS49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

CS128 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

CS180 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

Datasheet Information

List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

Export Administration Regulations (EAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

Revision 5

iii

1 – ex Automotive Family FPGAs

General Description

Based on a 0.22 µm CMOS process technology, the eX family of FPGAs is a low-cost solution for low-

power, high-performance designs. With the automotive temperature grade support (–40ºC to 125ºC), the

eX devices can address many in-cabin telematics and automobile interconnect applications. The low-

power attributes inherent in antifuse technology make the eX devices ideal for designers who are looking

to integrate low-density, power-sensitive automotive applications into a programmable logic solution,

enabling quick time-to-market.

eX Family Architecture

The eX family is implemented on a high-voltage twin-well CMOS process using 0.22 µm design rules.

The eX family architecture uses a “sea-of-modules” structure where the entire floor of the device is

covered with a grid of logic modules with virtually no chip area lost to interconnect elements or routing.

Interconnection among these logic modules is achieved using Microsemi’s patented metal-to-metal

programmable antifuse interconnect elements. The antifuse interconnect is made up of a combination of

amorphous silicon and dielectric material with barrier metals and has an "on" state resistance of 25

with a capacitance of 1.0 fF for low-signal impedance. The antifuses are normally open circuit and, when

programmed, form a permanent low-impedance connection. The eX family provides two types of logic

modules, the register cell (R-cell) and the combinatorial cell (C-cell).

The R-cell contains a flip-flop featuring asynchronous clear, asynchronous preset, and clock enable

(using the S0 and S1 lines) control signals (Figure

1-1).

The R-cell registers feature programmable clock

polarity selectable on a register-by-register basis. This provides additional flexibility while allowing

mapping of synthesized functions into the eX FPGA. The clock source for the R-cell can be chosen from

either the hardwired clock or the routed clock.

The C-cell implements a range of combinatorial functions up to five inputs (Figure

1-2 on page 1-2).

Inclusion of the DB input and its associated inverter function enables the implementation of more than

4,000 combinatorial functions in the eX architecture in a single module.

Two C-cells can be combined together to create a flip-flop to imitate an R-cell via the use of the CC

macro. This is particularly useful when implementing nontiming-critical paths and when the design

engineer is running out of R-cells. For more information about the CC macro, refer to the

Maximizing

Logic Utilization in eX, SX and SX-A FPGA Devices Using CC Macros

application note.

Routed

Data Input S1

PSET

DirectConnect

Input

HCLK

CLKA,

CLKB,

Internal Logic

CKS

CKP

CLR

Figure 1-1 •

R-Cell

Revision 5

1 -1

Recommended Resources

High input impedance three op amp differential amplifier circuit diagram

CB3463 combined semi-automatic turret lathe electrical schematic circuit 04

Triangular wave-rectangular wave generator

Clever use of KD-28 as a karaoke muffler circuit diagram

Same-line telephone switching circuit (2)

30MHZ antenna amplifier circuit

Our AVR - ATmega128L: Let's discuss how to learn ATmega128L well. . ....; tongyuan2007 Microchip MCU

my country's 3G talent gap will reach 500,000: In the next two to three years, China will enter the peak period of 3G infrastructure construction. However, behind the public's attention to the launch time of 3G and the issuance of 3G licenses, the...; mdsfnsa RF/Wirelessly

[Ask] About accidentally modifying pointer contents in a function: I have to bother you guys to discuss this again! Thank you in advance!When I designed the program, I used a function pointer to pass a structure pointer Item to the corresponding function. However, in...; lijun0209 stm32/stm8

SCI sends 16-bit data: My AD collects 16-bit signed integers, and I want to send them through the serial port. However, after SCI programming, the data received is only the lower 8 bits of the 16-bit data. How should I modi...; szxgl Microcontroller MCU

51 chip???? Oops!!!!!! Actually I hate it: I have used 51 chips for a long time. I was very dissatisfied with its power consumption. However, because its price is getting cheaper and cheaper, and its cost performance is still very good, I can'...; rain 51mcu

[National Technology N32 MCU Development Package] -- N32G435 Series: [attach]605054[/attach] [attach]605053[/attach][attach]]605049[/attach][attach]605047[/attach][attach]605044[/attach][attach]605051[/attach] [attach]605050[/attach][attach]605047[/attach][attach ]6050...; milafan Domestic Chip Exchange

Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

Popular Components