TB62702P/F
TOSHIBA Bi−CMOS INTEGRATED CIRCUIT SILICON MONOLITHIC
TB62702P,TB62702F
10BIT SERIAL−IN PARALLEL−OUT SHIFT REGISTER / LATCH / 10SEGMENT LED
DRIVERS
The TB62702P, TB62702F are specifically designed for
10−Segment LED Drivers and LED display. And these are
monolithic integrated circuits designed to be used together with
Bi−CMOS (DMOS) integrated circuit. The devices consist of a
10bit shift Register and 10bit Latches, and 10bit DMOS
structures.
TB62702P
FEATURES
10bit serial−in parallel−out shift register / latch / 10segment
LED driver (Bi−CMOS process)
CMOS compatible inputs
Open−drain DMOS outputs
Low steady−state power consumption
Serial data output for cascade operation
Packge ; P−type DIP−20−P−300A
F−type SOP−20−P−300
Weight
DIP20-P-300-2.54A: 2.25 g (typ.)
SOP20-P-300-1.27: 0.48 g (typ.)
TB62702F
PIN CONNECTION
(TOP VIEW)
1
2006-06-14
TB62702P/F
BLOCK DIAGRAM
ABSOLUTE MAXIMUM RATINGS
(Ta = 25°C, V
SS
= 0 V)
CHARACTERISTIC
Supply Voltage
Input Voltage
Output Drain−Source Voltage
Output Current
Power Dissipation
Operating Temperature
Storage Temperature
P
F
SYMBOL
V
DD
V
IN
V
OUT
I
OUT
P
D
(Note 1)
T
opr
T
stg
RATING
−0.3~7.0
−0.3~V
DD
+0.3
−0.4~30
30
1.47
0.96 (Note 2)
−40~85
−55~150
UNIT
V
V
V
mA / bit
W
°C
°C
Note 1: Delated above 25°C in the proportion of 11.7 mW / °C(P−type),
7.7 mW / °C(F−type).
Note 2: On Glass Epoxy (50 × 50 × 1.6mm Cu 40%)
2
2006-06-14
TB62702P/F
RECOMMENDED OPERATING CONDITIONS
(Ta =
−40~85°C,
V
SS
= 0 V)
CHARACTERISTIC
Supply Voltage
"H" Level
Input Voltage
"L" Level
Output Drain−Source Voltage
Output Current
Power Dissipation
P
F
V
IL
V
OUT
I
OUT
P
D
―
―
Duty = 100%, All output on
―
(Note 1)
SYMBOL
V
DD
V
IH
CONDITION
―
―
MIN
4.5
0.7
V
DD
0
―
―
―
―
TYP.
5
―
―
―
―
―
―
MAX
5.5
V
DD
0.3
V
DD
30
24
760
470
V
UNIT
V
V
mA /
ch
mW
Note 1: On Glass Epoxy (50 × 50 × 1.6 mm Cu 40%)
ELECTRICAL CHARACTERISTICS
(Ta =
−40
~
85°C, V
DD
= 4.5
~
5.5 V, V
SS
= 0 V)
CHARACTERISTIC
"L" Level
Output Voltage
"L" Level
"L" Level
"L" Level
Output Resistor
SYMBOL
V
DS1
V
DS1
V
DS2
V
DS2
R
ON
I
OZ1
Output Leakage Current
I
OZ2
Input Current
"H" Level
Output Current
"L" Level
"H" Level
Input Voltage
"L" Level
Operating Supply Current
Standby Supply Current
V
IL
I
DD1
I
DD2
―
―
―
―
f
CLK
= 5 MHz
NO loads, 1 bit
―
I
OL
V
IH
―
―
I
IN
I
IL
I
OH
―
―
―
―
TEST
CIR−
CUIT
―
―
―
―
―
―
TEST CONDITION
I
OUT
= 15 mA, Ta = 25°C
I
OUT
= 15 mA
I
OUT
= 26 mA, Ta = 25°C
I
OUT
= 26 mA
Ta = 25°C, I
OUT
= 26 mA
V
OUT
= 30 V, EN = "L"
1 bit
V
OUT
= 30 V, EN = "L"
10 bit
V
IN
= V
DD
or V
SS
ENABLE, V
IN
= V
SS
S−OUT
V
DS
= 4.6 V, V
DD
= 5.0 V
S−OUT
V
DS
= 0.4 V, V
DD
= 5.0 V
―
MIN
―
―
―
―
―
―
―
―
−27.5
−400
400
0.7
V
DD
0
―
―
TYP.
―
―
―
―
―
―
―
―
−55.0
−600
600
―
―
―
―
MAX
0.18
0.27
0.31
0.47
12
10
µA
±1
±1
−110.0
―
µA
―
V
DD
0.3
V
DD
1500
500
V
µA
Ω
V
UNIT
µA
3
2006-06-14
TB62702P/F
SWITCHING CHARACTERISTICS
CHARACTERISTIC
CLK−
OUTn
Propagation Delay
Time (Low−to−High)
(Ta = 25°C, V
DD
= 5 V, V
OUT
= 30 V, R
L
= 1150
Ω,
C
L
= 15 pF, "H" = V
IH
, "L" = V
IL
)
SYMBOL
TEST CONDITION
LAT = "H",
CLR = "H", EN = "H"
t
pLH
LAT = "H", EN = "H"
MIN
―
―
TYP.
―
―
MAX
250
250
UNIT
CLK− OUTn
LAT
−
OUTn
CLR = "H", EN = "H"
LAT = "H", CLR = ”H”
LAT = "H", CLR = "H", EN = "H"
―
―
―
―
―
―
―
―
―
―
200
150
250
200
150
ns
EN− OUTn
CLK− OUTn
Propagation Delay
Time (High−to−Low)
LAT
−
OUTn
EN− OUTn
t
pHL
CLR = "H", EN = "H"
LAT = "H", CLR = "H"
ns
Set Up Time
CLK−
LAT
t
setup (L)
t
setup (D)
t
hold (L)
t
hold (D)
t
w CLK
t
w
LAT
t
w
CLR
t
w EN
t
or
t
r
t
of
t
f
f
MAX1
f
MAX2
OUTn
S−OUT, V
SS
= 0V
OUTn
S−OUT, V
SS
= 0V
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
5
6
―
―
―
―
―
―
―
―
―
―
―
―
8
12
50
35
105
50
100
50
50
400
1000
50
150
50
―
―
MHz
ns
ns
ns
CLK−S−IN
CLK− LAT
CLK−S−IN
Hold Time
Clock Pulse Width
Latch Pulse Width
Clear Pulse Width
Enable Pulse Width
Output Rise Time
Output Fall Time
Maximum Clock Frequency
Duty = 50%
Cascade connected
Duty = 50%
RECOMMENDED TIMING CONDITIONS
(Ta =
−40
~
85°C, V
DD
= 4.5
~
5.5 V, V
SS
= 0)
CHARACTERISTIC
Clock Pulse Width
Enable Pulse Width
Latch Pulse Width
Clear Pulse Width
Data Set Up Time
Data Hold Time
SYMBOL
t
w CLK
t
w EN
t
w LAT
t
w
CLR
t
setup
t
hold
TEST CONDITION
―
―
―
―
―
―
MIN
100
400
100
100
100
150
TYP.
―
―
―
―
―
―
MAX
―
―
―
―
―
―
UNIT
ns
µs
ns
ns
ns
ns
4
2006-06-14
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