1. Features
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Management of 16 inputs-outputs (16-bit or two 8-bit configurable ports)
VAN protocol V4.0
3 external wired address
Safety mode in case of transmission loss
Automatic adaptation to speed of bus from 8kTS/s to 250kTS/s
CMOS 0,5
μ
m, IO CMOS TTL compatible
Internal power-on-reset
Internal ring oscillator from 10 to 40MHz (for internal clock)
500kHz oscillator with external RC network (for safety mode clock usage)
Supply voltage 5V±10%
Typical power consomption 4mA
SO28 package
VAN Peripheral
Circuit
16 Inputs-Outputs
TSSIO16E
Rev. 4421B–ASSP–10/05
2. General Description / Block Diagram
The block diagram given below shows the organization of the circuit as two blocks: the VAN con-
troller (block 1), and the groups of specific functions (block 2) relative to the TSSIO16E. These
are based on management of 16 inputs-outputs grouped together to form two 8-bit bi-directional
programmable ports: port A and port B. The circuit thus ensures double exchange of informa-
tion with the VAN bus (via the line interface) on the one hand and the active environment on the
other.
The bus data is supplied to the circuit (after shaping by the line transmitter/receiver) through 3
input lines RXD0, RXD1 and RXD2 selected one after another when communication on one of
the lines is defective (line diagnosis system). Operation outside of the RXD0 line is referred to
as in
degrated mode.
If perturbations persist in reception the circuit switches to the
safety
mode (INT = 1)
which, by default, ensures safety functions by activating or inhibiting external cir-
cuitry. Two CONTROL and STATUS 8-bit registers, are used respectively for setting operation
to a given configuration, and for diagnosing the state of the circuit.
The write and read modes of ports A and B are determined by decoding the local address of the
identifier field in the VAN frame.
The behaviour of each port can be configured by three registers: DATA, DDR (Data Direction
Register) and OPT (Option Register).
External address decoding by 3 pins produces 8 TSSIO16E circuits on the same bus.
2
TSSIO16E
4421B–ASSP–10/05
TSSIO16E
3. Pinout / Package
The pinout of the circuit is given below.
pin
13, 14, 15, 16,
17, 18, 19, 20
22, 23, 24, 25,
26, 27, 28, 1
2
3
4
5
6
7
8
9
12
11
10
21
name
PA[0..7]
I/O
I/O
description
Port A, 8 bi-directional bits, TTL compatible, Schmitt trigger
PB[0..7]
H500
TSTb
AD1
AD2
AD3
RXD1
RXD2
RXD0
INT
TXD
VSS
VDD
I/O
I/O
I
I
I
I
I
I
I
O
O
Port B event type, 8 bi-directional bits, TTL compatible, Schmitt trigger
Safety mode clock connection to ground or connection of a RC dipole for
500kHz oscillator.
In application, this input is tied to 1. In test mode, this input is tied to 0. TTL
compatible with pull-up.
External wired address - TTL compatible.
Receives output of comparator controlled by the
Data signal
from the
interface circuit. TTL compatible
Receiving the output of the comparator driven by the
Data_B signal
of
the interface circuit. TTL compatible.
Receives the comparator output driven by the differential (
Data signal
-
Data_B
).of the interface circuit. TTL compatible.
Interrupt. Used to generate an external active safety mode. TTL
compatible.
Drives the line interface circuit. TTL compatible.
Ground.
External power supply.
The package is SO28.
3
4421B–ASSP–10/05
4. Functional Features
4.1
Content of Identifier Field
The TSSIO16E circuit identifier field is structured as shown below.
External wired address
Identifier field
(undecoded)
Local address
The local address consists of bits I1, I2 and I3 of the identifier field for the VAN frame addressing
the circuit, the Bit I1 indicates reading or writing. The table below gives the significance of these
bits.
I3
0
0
0
0
1
1
1
1
I2
0
0
1
1
0
0
1
1
I1
0
1
0
1
0
1
0
1
local address
0
1
2
3
4
5
6
7
action
writing of VAN CONTROL register
reading of VAN STATUS register (RANK 16)
writing of port A
reading of port A (RANK 16)
writing of port AB
reading of port AB (RANK 16)
writing of port B
reading of port B (RANK 16)
4.2
Addressing of ports A and B and of COMMAND and STATUS registers
The specific functions of the circuit are activated by the selection of one or two ports depending
on the local address decoding (see § 4.1) as contained in the identifier field of the VAN frame
received by the circuit and by the content of the data bytes for this frame.
4.2.1
Local address 0 and 1
I3
Writing of the COMMAND register
Reading of the STATUS register
0
0
I2
0
0
I1
0
1
Writing and reading of these registers are described in paragraph 4.4.
The writing of the COMMAND register uses a single data byte. The reading of the STATUS reg-
ister sends a data byte to RANK 16.
4
TSSIO16E
4421B–ASSP–10/05
TSSIO16E
4.2.2
Local address 2 and 3
I3
Writing of port A
0
I2
1
I1
0
The writing of port A must be carried out with 1, 2 or 3 data bytes, otherwise the frame will not be
acknowledged and not taken into consideration. If writing uses a single byte, the port will be set
as output and output the DATA_A value. The automobile environment is thus affected by inter-
ference (possibility of deprogramming), it is advisable to write to ports A and B systematically
using 3 bytes.
DATA_A
or
DATA_A
DDR_A
or
DATA_A
DDR_A
OPT_A
DATA_A :
DDR_A :
OPT_A :
Output byte value for port A.
Defines, bit by bit, the direction of the I/O pins for port A (0 = input, 1 = output).
Unused register, this register must be forced to 0.
I3
Reading of port A
0
I2
1
I1
1
A read frame RANK16 at local address 3 recovers the data byte present on port A wether the
direction is input or output.
4.2.3
Local address 4 and 5
I3
Writing of port A and B
1
I2
0
I1
0
A write frame for port A and B contains 6 bytes. The management of the DATA, DDR and OPT
bytes is the same as in the case of port A alone.
DATA_A
DDR_A
OPT_A
DATA_B
DDR_B
OPT_B
OPT_B register must be forced to 0.
I3
Reading of port A and B
1
I2
0
I1
1
5
4421B–ASSP–10/05
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