19-3103; Rev 0; 12/07
Multirate CDR with Integrated Serializer/Deserializer
for GPON and BPON ONT Applications
General Description
The MAX3886 2.488Gbps/1.244Gbps/622Mbps CDR
with SerDes (serializer/deserializer) is designed specifi-
cally for low-cost optical network terminal (ONT) appli-
cations in Gigabit passive optical network (GPON) and
broadband passive optical network (BPON) fiber-to-
the-home (FTTH) systems. It provides G.984- and
G.983-compliant clock and data recovery (CDR) for the
continuous downstream data signal, with an integrated
4-bit SerDes that has LVDS parallel interfaces and CML
serial interfaces.
The SerDes uses the recovered downstream clock for
upstream serialization (loopback clock), providing opti-
mum PON operation. The CDR frequency reference
can be provided by a low-cost 19.44MHz SMD-type
crystal or external LVCMOS source, and excellent jitter
tolerance supports applications requiring FEC. An inte-
grated burst-enable signal path also simplifies high-
performance upstream burst timing.
This 3.3V IC is housed in a 8mm x 8mm, 56-lead thin
QFN package and operates from -40°C to +85°C.
Features
♦
2.488Gbps, 1.244Gbps, and 622Mbps Clock and
Data Recovery
♦
Meets G.984 and G.983 Jitter Requirements
♦
4-Bit Serializer and 4-Bit Deserializer with
Loop-Timed Serialization
♦
CML Serial I/O, LVDS Parallel I/O
♦
Integrated Reference Oscillator Uses 19.44MHz
SMD Crystal
♦
Integrated Upstream Burst-Enable Signal Path
MAX3886
Ordering Information
PART
MAX3886ETN+
TEMP RANGE
-40°C to +85°C
PIN-
PACKAGE
56 TQFN
(8mm x 8mm)
PKG
CODE
T5688-2
+Denotes
a lead-free package.
Applications
BPON/GPON Optical Network Terminal (ONT)
Pin Configuration appears at end of data sheet.
Typical Application Circuit
+3.3V
+3.3V
0.27μF
V
CC
RFCK1
19.4400MHz
MAX3747/ 2.488G
MAX3748
LIM AMP
1310nm MAX3643/
MAX3656
LD DRIVER
RFCK2
SDI
CFIL
V
CC
MVCO
MDDR
MSYM
MAC IC
+3.3V
VOICE
SLIC
MAX3886
GPON
CDR/SERDES
PCLK (311MHz)
PDATA (622Mbps)
PDATA (311Mbps)
PCLK (311MHz)
BURST ENABLE
DATA
10/100
ETHERNET
1490nm
PON
BiDi
TRIPLEXER
PCKO
PDO[3:0]
PDI[3:0]
1.244G
SDO
PCKI
BENO
BENI
GND LOCK FRST FERR
1550nm
MAX3654
VIDEO TIA
GPON OPTICAL NETWORK TERMINAL (ONT)
870MHz VIDEO
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Multirate CDR with Integrated Serializer/Deserializer
for GPON and BPON ONT Applications
MAX3886
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Range (V
CC
).................................-0.3V to +4.0V
CML Input Voltage Range (SDI±)...............-0.3V to (V
CC
+ 0.3V)
CML Output Current (SDO±, BENO±)...............................±22mA
LVDS Input Voltage Range
(PCKI±, PDI[3:0]±, BENI±)......................-0.3V to (V
CC
+ 0.3V)
LVDS Output Voltage Range
(RCKO±, PDO[3:0]±, PCKO±) ................-0.3V to (V
CC
+ 0.3V)
LVCMOS Input Voltage Range
(MSYM, MDDR, FRST)............................-0.3V to (V
CC
+ 0.3V)
Three-State Input Voltage Range
(MVCO)...................................................-0.3V to (V
CC
+ 0.3V)
LVCMOS Output Voltage Range
(LOCK, FERR) ........................................-0.3V to (V
CC
+ 0.3V)
Voltage Range at CFIL, RFCK1,
RFCK2, TP1, TP2, TP3, TP4 ...................-0.3V to (V
CC
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
56-Pin TQFN (derate 47.6mW/°C above 70°C)..........3808mW
Operating Junction Temperature Range ...........-55°C to +150°C
Storage Temperature Range .............................-55°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
OPERATING CONDITIONS
PARAMETER
Operating Temperature
Power-Supply Voltage
Downstream/Upstream
Data Rates
Reference Frequency
Crystal Accuracy
Crystal ESR
Crystal Drive
Crystal Load Capacitance
Reference Clock Input Duty
Cycle
On-chip parallel capacitance
When driven by an LVCMOS clock source
40
18
60
Internal or external oscillator
Includes aging, temperature, and other
contributors
Fundamental type, AT-strip cut
10
SYMBOL
T
A
V
CC
CONDITIONS
MIN
-40
3.0
See Table 2
19.4400
±250
60
100
μW
pF
%
TYP
MAX
+85
3.6
UNITS
°C
V
Gbps
MHz
ppm
ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, T
A
= -40°C to +85°C. Typical values are at V
CC
= +3.3V, T
A
= +25°C, unless otherwise noted. LVDS outputs
terminated 100Ω differential, CML inputs terminated 100Ω differential, CML outputs terminated 100Ω differential.) (Note 1)
PARAMETER
Supply Current
SYMBOL
I
CC
MVCO = 1
Serial Input Data Rate
CDR CID Immunity
CDR Sinusoidal Jitter Tolerance
SDI to SDO Jitter Transfer
f > f
C
Rate
MVCO = open
MVCO = 0
BER
BER
10
-10
(Note 2)
10
-10
(Note 3)
0.3
CONDITIONS
MIN
TYP
240
2488.32
1244.16
622.08
> 100
0.7
0.1
Bits
UI
P-P
dB
Mbps
MAX
310
UNITS
mA
CDR/DESERIALIZER SPECIFICATIONS
(Notes 4, 5)
2
_______________________________________________________________________________________
Multirate CDR with Integrated Serializer/Deserializer
for GPON and BPON ONT Applications
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +3.0V to +3.6V, T
A
= -40°C to +85°C. Typical values are at V
CC
= +3.3V, T
A
= +25°C, unless otherwise noted. LVDS outputs
terminated 100Ω differential, CML inputs terminated 100Ω differential, CML outputs terminated 100Ω differential.) (Note 1)
PARAMETER
SDI to SDO Jitter Transfer
Bandwidth
Parallel Clock Output Random
Jitter
Parallel-Output Clock to Data
Time
Parallel Clock and Data-Output
Rise/Fall Time
Parallel-Clock Output Duty
Cycle
Parallel-Clock Output Frequency
Parallel-Data Output
Channel-to-Channel Skew
CDR Acquisition Time
(After Startup)
Reference-Output Clock
Frequency
SERIALIZER SPECIFICATIONS
Parallel-Input Clock Frequency
Serial-Output Data Rate
Parallel-Data Input-Setup Time
Parallel-Data Input-Hold Time
Serial-Data Output Rise/Fall
Time
Serial-Data Output Random Jitter
Serial-Data Output
Deterministic Jitter
Burst Enable to Serial Data
MSB Time
Minimum Pulse Width of
FIFO Reset
Tolerated Drift Between PCKI
and PCKO After FIFO Reset
I/O SPECIFICATIONS
CML Differential Input Voltage
CML Input Common-Mode
Range
V
IN
200
V
CC
-
1.49
V
CC
-
1.32
1600
V
CC
-
V
IN
/4
mV
P-P
V
t
B-MSB
t
SU
t
HD
t
r
, t
f
Figure 1
Figure 1
20% to 80%
(Notes 5, 6)
(Notes 2, 5)
Figure 2
UI is PCKO period
UI is PCKO period
-50
4
±1
170
300
160
4
47
+50
See Table 2
See Table 2
MHz
Mbps
ps
ps
ps
mUI
RMS
mUI
P-P
ps
UI
UI
2
See Table 2
t
CK-Q
t
r
, t
f
SYMBOL
(Notes 3, 4)
(Note 6)
Figure 1
20% to 80%
45
See Table 2
100
-80
< 0.5
+80
300
55
CONDITIONS
MIN
TYP
MAX
f
C
UNITS
MHz
mUI
RMS
ps
ps
%
MHz
ps
ms
MHz
MAX3886
_______________________________________________________________________________________
3
Multirate CDR with Integrated Serializer/Deserializer
for GPON and BPON ONT Applications
MAX3886
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +3.0V to +3.6V, T
A
= -40°C to +85°C. Typical values are at V
CC
= +3.3V, T
A
= +25°C, unless otherwise noted. LVDS outputs
terminated 100Ω differential, CML inputs terminated 100Ω differential, CML outputs terminated 100Ω differential.) (Note 1)
PARAMETER
CML Differential Output
CML Differential Output
Resistance
LVDS Input Voltage Range
LVDS Differential Input Range
LVDS Differential Input
Resistance
LVDS Output Voltage High
LVDS Output Voltage Low
LVDS Output Differential Voltage
LVDS Output Offset Voltage
LVDS Output Change in V
OD
LVDS Output Change in V
OS
LVDS Differential Output
Resistance
LVCMOS Input Voltage Low
LVCMOS Input Voltage High
LVCMOS Input Current
Three-State Input Current
LVCMOS Output Voltage Low
LVCMOS Output Voltage High
V
OL
V
OH
V
IL
V
IH
V
IH
= V
CC
or V
IL
= ground
MVCO input, V
IH
= V
CC
or V
IL
= ground
I
OL
= 100μA
I
OH
= -100μA
2.0
-10
-50
V
CC
-
0.2
+10
+50
0.2
V
OD
V
OS
| V
OD
|
| V
OS
|
Figure 3
V
OS
= (V
OUT+
+ V
OUT-
)/2, Figure 3
Between “0” and “1”
Between “0” and “1”
80
100
925
250
1125
400
1275
25
25
140
0.8
V
V
μA
μA
V
V
(Note 5)
SYMBOL
CONDITIONS
MIN
640
80
0
±100
80
100
TYP
800
100
MAX
1000
120
2400
±600
120
1475
mV
mV
mV
mV
mV
mV
mV
mV
UNITS
mV
P-P
Note 1:
With a 19.4400MHz SMD AT-strip crystal at RFCK1 and RFCK2.
Note 2:
Pattern is 16 x 2
7
- 1 PRBS, 100 CIDs, 16 x 2
7
- 1 PRBS inverted, 100 CIDs inverted.
Note 3:
For 622Mbps operation, f
C
= 500kHz.
For 1.244Gbps operation, f
C
= 1MHz.
For 2.488Gbps operation, f
C
= 2MHz.
Note 4:
Jitter transfer from SDI to SDO, with parallel side looped back. Defined as:
⎡
jitter on upstream signal UI
downstream bit rate
⎤
×
Jitter transfer
= ⎢
⎥
upstream bit rate
⎥
⎢
jitter on downstream signal UI
⎦
⎣
Note 5:
Guaranteed by design and characterization.
Note 6:
For 2.488Gbps operation, measurement bandwidth = 8kHz to 20MHz.
For 1.244Gbps operation, measurement bandwidth = 4kHz to 10MHz.
For 622Mbps operation, measurement bandwidth = 2kHz to 5MHz.
For 155Mbps operation, measurement bandwidth = 0.5kHz to 1.3MHz.
4
_______________________________________________________________________________________
Multirate CDR with Integrated Serializer/Deserializer
for GPON and BPON ONT Applications
MAX3886
1UI
SDO
PDO_
PDI1
PDI0
PDI3
PDI2
PDI1
PCKO
(MDDR = 0)
BENO
t
B-MSB MIN
t
B-MSB MAX
PCKO
(MDDR = 1)
t
CK-Q MIN
t
CK-Q MAX
Figure 2. Burst-Enable Timing
1UI
PDI_
PCKI
t
SU
t
HD
Figure 1. Parallel Interface Timing Diagrams
LVDS
R
L
= 100Ω
V
V
OD
V
OUT-
SINGLE- ENDED OUTPUT
V
OUT+
V
OD
V
OS
+V
OD
DIFFERENTIAL OUTPUT
0V
-V
OD
V
OD(P-P)
= V
OUT+
- V
OUT-
Figure 3. Definition of LVDS Output Levels
_______________________________________________________________________________________
5
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