STA517B
60 V 6 A quad power half bridge
Features
■
■
■
■
■
■
Minimum input output pulse width distortion
200 mΩ R
dsON
complementary DMOS output
stage
CMOS compatible logic inputs
Thermal protection
Thermal warning output
Under voltage protection
Power SO36 slug up
Description
STA517B is a monolithic quad half bridge stage in
Multipower BCD Technology. The device can be
used as dual bridge or reconfigured, by
connecting CONFIG pin to Vdd pin, as single
bridge with double current capability, and as half
bridge (Binary mode) with half current capability.
The device is particularly designed to make the
output stage of a stereo all-digital high efficiency
(DDX™) amplifier capable to deliver 175 + 175 W
@ THD = 10 % at V
cc
54 V output power on 8
Ω
load and 350 W @ THD = 10 % at V
cc
54 V on
4
Ω
load in single BTL configuration.
The input pins have threshold proportional to V
L
pin voltage.
Table 1.
Device summary
Part number
STA517B
STA517B13TR
Package
Power SO36 slug up
Power SO36 slug up
Packaging
Tube
Tape and reel
March 2007
Rev 2
1/13
www.st.com
1
Contents
STA517B
Contents
1
2
3
4
5
6
7
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Power supply and control sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Mechanical and package data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2/13
STA517B
Introduction
1
Introduction
Figure 1.
Application circuit (dual BTL)
V
CC
1A
IN1A
IN1A
+3.3V
V
L
CONFIG
PWRDN
R57
10K
R59
10K
C58
100nF
TH_WAR
IN1B
V
DD
V
DD
V
SS
V
SS
C58
100nF
C53
100nF
C60
100nF
IN2A
V
CC
SIGN
V
CC
SIGN
IN2A
GND-Reg
GND-Clean
21
22
33
34
M17
35
8
9
36
31
20
19
M16
M15
REGULATORS
7
V
CC
2A
C32
1µF
OUT2A
OUT2A
6
GND2A
PWRDN
FAULT
23
24
25
27
26
TRI-STATE
PROTECTIONS
&
LOGIC
M5
28
30
M4
13
M2
29
M3
15
17
16
C30
1µF
OUT1A
OUT1A
14
GND1A
C52
330pF
+V
CC
C55
1000µF
L18 22µH
C20
100nF
R98
6
C99
100nF
C23
470nF
C101
100nF
8Ω
12
V
CC
1B
C31
1µF
OUT1B
OUT1B
GND1B
R63
20
R100
6
C21
100nF
L19 22µH
11
10
TH_WAR
IN1B
L113 22µH
C110
100nF
C109
330pF R103
6
R104
20
4
V
CC
2B
C33
1µF
OUT2B
OUT2B
R102
6
C111
100nF
3
2
C107
100nF
C108
470nF
C106
100nF
8Ω
IN2B
IN2B
GNDSUB
32
M14
L112 22µH
1
5
GND2B
D00AU1148B
3/13
Pin lists
STA517B
2
Pin lists
Table 2.
Number
1
2, 3
4
5
6
7
8, 9
10, 11
12
13
14
15
16, 17
18
19
20
21, 22
23
24
25
26
27
28
29
30
31
32
33, 34
35, 36
Pin function
Pin
GND-SUB
OUT2B
VCC2B
GND2B
GND2A
VCC2A
OUT2A
OUT1B
VCC1B
GND1B
GND1A
VCC1A
OUT1A
NC
GND-CLEAN
GND-REG
VDD
V
L
CONFIG
PWRDN
TRI-STATE
FAULT
TH-WAR
IN1A
IN1B
IN2A
IN2B
VSS
VCC SIGN
Substrate ground
Output half bridge 2B
Positive supply
Negative supply
Negative supply
Positive supply
Output half bridge 2A
Output half bridge 1B
Positive supply
Negative supply
Negative supply
Positive supply
Output half bridge 1A
Not connected
Logical ground
Ground for regulator Vdd
5 V regulator referred to ground
High logical state setting voltage
Configuration pin
Stand-by pin
Hi-Z pin
Fault pin advisor
Thermal warning advisor
Input of half bridge 1A
Input of half bridge 1B
Input of half bridge 2A
Input of half bridge 2B
5 V regulator referred to +Vcc
Signal positive supply
Description
4/13
STA517B
Table 3.
Pin name
FAULT
FAULT
(1)
TRI-STATE
TRI-STATE
PWRDN
PWRDN
THWAR
THWAR
(
1
)
CONFIG
CONFIG
(2)
0
1
0
1
0
1
0
1
0
1
Pin lists
Functional pin status
Logical value
Status
Fault detected (short circuit or thermal for example)
Normal operation
All powers in Hi-Z state
Normal operation
Low absorption
Normal operation
Temperature of the IC =130
o
C
Normal operation
Normal operation
OUT1A=OUT1B; OUT2A=OUT2B
(IF IN1A = IN1B; IN2A = IN2B)
1. The pin is open collector. To have the high logic value, it needs to be pulled up by a resistor.
2. CONFIG = 1 means connect Pin 24 (CONFIG) to Pins 21, 22 (Vdd)
Figure 2.
Pin connection
V
CC
Sign
V
CC
Sign
V
SS
V
SS
IN2B
IN2A
IN1B
IN1A
TH_WAR
FAULT
TRI-STATE
PWRDN
CONFIG
VL
VDD
VDD
GND-Reg
GND-Clean
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
D01AU1273
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
GND-SUB
OUT2B
OUT2B
V
CC
2B
GND2B
GND2A
V
CC
2A
OUT2A
OUT2A
OUT1B
OUT1B
V
CC
1B
GND1B
GND1A
V
CC
1A
OUT1A
OUT1A
N.C.
5/13