82V3385PF datasheet, PDF - EEWORLD Datasheet

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82V3385PF: DescriptionTelecom Circuit, 1-Func, PQFP100, TQFP-100; CategoryWireless rf/communication Telecom circuit; File Size1MB，184 Pages; ManufacturerIDT (Integrated Device Technology)

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82V3385PF Overview

Telecom Circuit, 1-Func, PQFP100, TQFP-100

82V3385PF Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	QFP
package instruction	QFP, QFP100,.63SQ,20
Contacts	100
Reach Compliance Code	not_compliant
Is Samacsys	N
JESD-30 code	S-PQFP-G100
JESD-609 code	e0
length	14 mm
Humidity sensitivity level	3
Number of functions	1
Number of terminals	100
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Encapsulate equivalent code	QFP100,.63SQ,20
Package shape	SQUARE
Package form	FLATPACK
Peak Reflow Temperature (Celsius)	240
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum slew rate	0.528 mA
Nominal supply voltage	3.3 V
surface mount	YES
Telecom integrated circuit types	TELECOM CIRCUIT
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	20
width	14 mm
Base Number Matches	1

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SYNCHRONOUS ETHERNET

WAN PLL

IDT82V3380

NRND - Not Recommend for New Designs

FOR REPLACEMENT DEVICE USE IDT82V3380A

Version 3

October 12, 2012

6024 Silver Creek Valley Road, San Jose, CA 95138

Telephone: (800) 345-7015 • TWX: 910-338-2070 • FAX: (408) 284-2775

Printed in U.S.A.

Table of Contents

NRND - Not Recommend for New Designs

FEATURES .............................................................................................................................................................................. 9

HIGHLIGHTS.................................................................................................................................................................................................... 9

MAIN FEATURES ............................................................................................................................................................................................ 9

OTHER FEATURES ......................................................................................................................................................................................... 9

APPLICATIONS....................................................................................................................................................................... 9

DESCRIPTION....................................................................................................................................................................... 10

FUNCTIONAL BLOCK DIAGRAM ........................................................................................................................................ 11

1 PIN ASSIGNMENT ........................................................................................................................................................... 12

2 PIN DESCRIPTION .......................................................................................................................................................... 13

3 FUNCTIONAL DESCRIPTION ......................................................................................................................................... 19

RESET ........................................................................................................................................................................................................... 19

MASTER CLOCK .......................................................................................................................................................................................... 19

INPUT CLOCKS & FRAME SYNC SIGNAL ................................................................................................................................................. 20

3.3.1 Input Clocks .................................................................................................................................................................................... 20

3.3.2 Frame SYNC Input Signals ............................................................................................................................................................ 20

3.4 INPUT CLOCK PRE-DIVIDER ...................................................................................................................................................................... 21

3.5 INPUT CLOCK QUALITY MONITORING ..................................................................................................................................................... 23

3.5.1 LOS Monitoring .............................................................................................................................................................................. 23

3.5.2 Activity Monitoring ......................................................................................................................................................................... 23

3.5.3 Frequency Monitoring ................................................................................................................................................................... 24

3.6 T0 / T4 DPLL INPUT CLOCK SELECTION .................................................................................................................................................. 25

3.6.1 External Fast Selection (T0 only) .................................................................................................................................................. 25

3.6.2 Forced Selection ............................................................................................................................................................................ 26

3.6.3 Automatic Selection ....................................................................................................................................................................... 26

3.7 SELECTED INPUT CLOCK MONITORING .................................................................................................................................................. 27

3.7.1 T0 / T4 DPLL Locking Detection ................................................................................................................................................... 27

3.7.1.1 Fast Loss .......................................................................................................................................................................... 27

3.7.1.2 Coarse Phase Loss .......................................................................................................................................................... 27

3.7.1.3 Fine Phase Loss ............................................................................................................................................................... 27

3.7.1.4 Hard Limit Exceeding ....................................................................................................................................................... 27

3.7.2 Locking Status ............................................................................................................................................................................... 27

3.7.3 Phase Lock Alarm (T0 only) .......................................................................................................................................................... 28

3.8 SELECTED INPUT CLOCK SWITCH ........................................................................................................................................................... 29

3.8.1 Input Clock Validity ........................................................................................................................................................................ 29

3.8.2 Selected Input Clock Switch ......................................................................................................................................................... 29

3.8.2.1 Revertive Switch ............................................................................................................................................................... 29

3.8.2.2 Non-Revertive Switch (T0 only) ........................................................................................................................................ 30

3.8.3 Selected / Qualified Input Clocks Indication ................................................................................................................................ 30

3.9 SELECTED INPUT CLOCK STATUS VS. DPLL OPERATING MODE ....................................................................................................... 31

3.9.1 T0 Selected Input Clock vs. DPLL Operating Mode .................................................................................................................... 31

3.9.2 T4 Selected Input Clock vs. DPLL Operating Mode .................................................................................................................... 33

3.10 T0 / T4 DPLL OPERATING MODE ............................................................................................................................................................... 34

3.10.1 T0 DPLL Operating Mode .............................................................................................................................................................. 34

3.10.1.1 Free-Run Mode ................................................................................................................................................................ 34

3.10.1.2 Pre-Locked Mode ............................................................................................................................................................. 34

3.10.1.3 Locked Mode .................................................................................................................................................................... 34

3.1

3.2

3.3

Table of Contents

October 12, 2012

IDT82V3380

SYNCHRONOUS ETHERNET WAN PLL

3.11

3.12

3.13

3.14

3.15

3.16

3.17

4.1

5.1

5.2

5.3

5.4

5.5

3.10.1.3.1 Temp-Holdover Mode .................................................................................................................................... 34

3.10.1.4 Lost-Phase Mode ............................................................................................................................................................. 34

3.10.1.5 Holdover Mode ................................................................................................................................................................. 34

3.10.1.5.1 Automatic Instantaneous ............................................................................................................................... 35

3.10.1.5.2 Automatic Slow Averaged ............................................................................................................................. 35

3.10.1.5.3 Automatic Fast Averaged .............................................................................................................................. 35

3.10.1.5.4 Manual ........................................................................................................................................................... 35

3.10.1.5.5 Holdover Frequency Offset Read .................................................................................................................. 35

3.10.1.6 Pre-Locked2 Mode ........................................................................................................................................................... 35

3.10.2 T4 DPLL Operating Mode .............................................................................................................................................................. 35

3.10.2.1 Free-Run Mode ................................................................................................................................................................ 35

3.10.2.2 Locked Mode .................................................................................................................................................................... 35

3.10.2.3 Holdover Mode ................................................................................................................................................................. 35

T0 / T4 DPLL OUTPUT ................................................................................................................................................................................. 37

3.11.1 PFD Output Limit ............................................................................................................................................................................ 37

3.11.2 Frequency Offset Limit .................................................................................................................................................................. 37

3.11.3 PBO (T0 only) ................................................................................................................................................................................. 37

3.11.4 Phase Offset Selection (T0 only) .................................................................................................................................................. 37

3.11.5 Four Paths of T0 / T4 DPLL Outputs ............................................................................................................................................. 37

3.11.5.1 T0 Path ............................................................................................................................................................................. 37

3.11.5.2 T4 Path ............................................................................................................................................................................. 38

T0 / T4 APLL ................................................................................................................................................................................................. 39

OUTPUT CLOCKS & FRAME SYNC SIGNALS ........................................................................................................................................... 39

3.13.1 Output Clocks ................................................................................................................................................................................. 39

3.13.2 Frame SYNC Output Signals ......................................................................................................................................................... 44

MASTER / SLAVE CONFIGURATION ......................................................................................................................................................... 46

INTERRUPT SUMMARY ............................................................................................................................................................................... 47

T0 AND T4 SUMMARY ................................................................................................................................................................................. 47

POWER SUPPLY FILTERING TECHNIQUES ............................................................................................................................................. 48

MASTER / SLAVE APPLICATION ............................................................................................................................................................... 49

4 TYPICAL APPLICATION ................................................................................................................................................. 49

5 MICROPROCESSOR INTERFACE .................................................................................................................................. 50

EPROM MODE .............................................................................................................................................................................................. 51

MULTIPLEXED MODE .................................................................................................................................................................................. 52

INTEL MODE ................................................................................................................................................................................................. 54

MOTOROLA MODE ...................................................................................................................................................................................... 56

SERIAL MODE .............................................................................................................................................................................................. 58

6 JTAG ................................................................................................................................................................................ 60

7 PROGRAMMING INFORMATION .................................................................................................................................... 61

7.1

7.2

REGISTER MAP ............................................................................................................................................................................................ 61

REGISTER DESCRIPTION ........................................................................................................................................................................... 67

7.2.1 Global Control Registers ............................................................................................................................................................... 67

7.2.2 Interrupt Registers ......................................................................................................................................................................... 76

7.2.3 Input Clock Frequency & Priority Configuration Registers ....................................................................................................... 82

7.2.4 Input Clock Quality Monitoring Configuration & Status Registers ......................................................................................... 108

7.2.5 T0 / T4 DPLL Input Clock Selection Registers ........................................................................................................................... 122

7.2.6 T0 / T4 DPLL State Machine Control Registers ......................................................................................................................... 128

7.2.7 T0 / T4 DPLL & APLL Configuration Registers .......................................................................................................................... 130

7.2.8 Output Configuration Registers .................................................................................................................................................. 144

7.2.9 PBO & Phase Offset Control Registers ...................................................................................................................................... 154

7.2.10 Synchronization Configuration Registers ................................................................................................................................. 156

JUNCTION TEMPERATURE ...................................................................................................................................................................... 158

8 THERMAL MANAGEMENT ........................................................................................................................................... 158

8.1

Table of Contents

October 12, 2012

IDT82V3380

SYNCHRONOUS ETHERNET WAN PLL

9 ELECTRICAL SPECIFICATIONS .................................................................................................................................. 160

9.1

9.2

9.3

8.2

8.3

8.4

EXAMPLE OF JUNCTION TEMPERATURE CALCULATION ................................................................................................................... 158

HEATSINK EVALUATION .......................................................................................................................................................................... 158

TQFP EPAD THERMAL RELEASE PATH ................................................................................................................................................. 159

9.4

9.5

9.6

9.7

ABSOLUTE MAXIMUM RATING ................................................................................................................................................................ 160

RECOMMENDED OPERATION CONDITIONS .......................................................................................................................................... 160

I/O SPECIFICATIONS ................................................................................................................................................................................. 161

9.3.1 AMI Input / Output Port ................................................................................................................................................................ 161

9.3.1.1 Structure ......................................................................................................................................................................... 161

9.3.1.2 I/O Level ......................................................................................................................................................................... 161

9.3.1.3 Over-Voltage Protection ................................................................................................................................................. 163

9.3.2 CMOS Input / Output Port ............................................................................................................................................................ 163

9.3.3 PECL / LVDS Input / Output Port ................................................................................................................................................ 164

9.3.3.1 PECL Input / Output Port ................................................................................................................................................ 164

9.3.3.2 LVDS Input / Output Port ................................................................................................................................................ 166

JITTER & WANDER PERFORMANCE ....................................................................................................................................................... 167

OUTPUT WANDER GENERATION ............................................................................................................................................................ 170

INPUT / OUTPUT CLOCK TIMING ............................................................................................................................................................. 171

OUTPUT CLOCK TIMING ........................................................................................................................................................................... 172

.............................................................................................................................................................................................

PACKAGE DIMENSIONS....................................................................................................................................................

ORDERING INFORMATION................................................................................................................................................

178

179

180

184

Table of Contents

October 12, 2012

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