SMH4046
Preliminary Information
1
(See Last Page)
Hot-Swap, Active DC Output Control (ADOC
TM
) Power Manager with I
2
C lnterface
FEATURES & APPLICATIONS
•
Full voltage Control for hot-swap applications
-
Add-in Card insertion detection
-
Platform voltage detection
•
Universal FPGA configuration I/O pins
•
High Voltage and logic level enable outputs
•
Active control (ADOC
TM
) for three downstream
DC/DC converters with
±0.5%
accuracy
•
Margining of three DC/DC converters
•
Power-up sequencing of all supply voltages
•
Power-down sequencing in Forward or Reverse
•
UV and OV sensors per channel with
programmable reset and interrupt
•
Programmable glitch filter for all channels
•
Configuration may be locked
•
Auto monitoring of all channels and Ext Temp
•
I
2
C
TM
serial bus interface
•
Programmable slew rate control
•
Integrated 2K EEPROM
Applications
•
Monitor/Control Distributed and POL Supplies
•
Multi-voltage Processors, DSPs, ASICs used in
Telecom or server systems
INTRODUCTION
The SMH4046 is an all-inclusive power management
controller that integrates hot swap protection of three
positive-voltage supplies (+12V or less). In addition to
hot swapping three bus voltages, it provides
sequencing and Active DC Output Control (ADOC
TM
)
of three on-card DC-DC converters as used in blade
servers and Telecom systems. It can also upload
configuration code from the host to on-card FPGAs.
All six channels can cascade-sequence during power-
up in any order as set by either hardware or firmware;
and sequence down in forward or reverse order.
ADOC
TM
control of the three DC/DC converters
maintains their accuracy to within
±0.5%
of the set
point using an internal voltage reference. ADOC
TM
is
also included during “margining” to allow card-by-card
performance evaluation during production with
arbitrary setting within
±10%
in any combination.
A full set of monitoring and control features are
included, with user programmability that can be
locked. The SMH4046 uses the I
2
C bus interface for
programming and FPGA configuration.
Ejector
Switch
FS
TYPICAL APPLICATIONS DRAWING
BD_SEL1#
FPGA
5
FPGA_CFGDNE
FPGA_NSTS
PND1#
FS
VMA
TRIMA
PUPA
VCC5
VMB
TRIMB
PUPB
VMC
TRIMC
PUPC
VGATE5
47nF
HST_RST#
PND2#
CARD_5V
VCC3
VGATE3
VGG_CAP
1uF
HEALTHY#
CARD_V_VLD
Temp Sensor
EXT_TMP
1Vref
SCL A2 SDA
RESET
CARD_3V
VCC12
DRVREN#
CARD_12V
FAULT
IRQ
47nF
10
270k
47nF
DC/DC #1
TRIM
VOUT
OE
VIN
DC/DC #2
TRIM
VOUT
OE
VIN
TRIM
OE
VIN
DC/DC #3
VOUT
FPGA_NCFG
FPGA_DCLK
FPGA_DO
+3.3V
+5V
+12V
GND
TEMP
GND
GND
+5V
Vout1
Vout2
BOARD CONNECTOR
GND
GND
HST_PWR
G
D
S
PCI_RST#
BD_SEL#
SMH4046
D
G
S
HEALTHY#
S
G
D
•Hot swap
•ADOC
TM
•Pwr On/Off
Board 5V
•Cascade
•Sequence
•Monitor
Board 3.3V
•Margin
•I
2
C
Vout3
Board 12V
BUS CONNECTOR
Pre-
Charge
Circuit
Switch
PCI Interface ASIC
Bus
IRQ
FAULT
CARD RESET
Figure 1 – Applications Schematic using the SMH4046 Controller to hot swap and actively control the output
levels of three DC/DC Converters while providing power on/off, cascade sequencing and output margining.
Note: This is an applications example only. Some pins, components and values are not shown.
© SUMMIT
Microelectronics, Inc.
2004 • 1717 Fox Drive • San Jose CA 95131 • Phone 408 436-9890 • FAX 408 436-9897
The Summit Web Site can be accessed by “right” or “left” mouse clicking on the link:
http://www.summitmicro.com/
2082 1.7 08/23/04
1
SMH4046
Preliminary Information
VCC12 ( +6V to +14V)
5.0V
3.3V
2.0V
1.8V
1.5V
RESET
t
DPONA
t
DPONB
t
DPONC
t
DPOND
t
DPONE
t
DPONF
---
t
PTO
---
Figure 2 – Example Power Supply Cascade Sequencing and System Initialization Using the SMH4046
GENERAL DESCRIPTION
The SMH4046 is a fully integrated hot swap controller
intended for use on add-in cards that are hot swapped
from powered-on host platforms. The SMH4046
performs a variety of tasks starting with the validation
of proper card insertion and the presence of “in-spec”
voltages at the host platform interface.
Once the SMH4046 switches power on, it continues to
monitor the back-end power to the add-in card and the
host power supply. When programmed to do so, the
SMH4046 immediately asserts the RESET outputs
and powers-down the add-in card when the 12V, 5V or
3.3V supplies drop below a programmable UV or
above an OV threshold.
In addition to the power control for the add-in card, the
SMH4046 provides status signals that can be
employed by the host for the control of bus interface
components.
On-chip EEPROM memory can be used to store serial
ID numbers or other pertinent information for the
individual card or as general-purpose memory. The
FPGA configuration-interface provides a direct
interface for simplified access to the add-in card’s
FPGAs using the I
2
C interface.
The SMH4046 has the ability to monitor and sequence
up to six power supplies (Figure 1). The SMH4046 can
monitor the 12V input and the internal and external
temperature sensors.
The SMH4046 has four
operating modes: Power-on sequencing mode,
monitor and control mode using Active DC Output
Control (ADOC), supply margining mode using ADOC,
and Power-off sequencing mode.
Power-on sequencing can be initiated via the
HST_PWR pin or through the serial interface. In this
mode, the SMH4046 sequences the power supply
channels on in any order by activating the PUPx,
VGATE and DRVREN# outputs while monitoring the
respective converter and host voltages to ensure
correct cascading of the supplies. Cascade-
sequencing is the ability to hold off the next
sequenced supply until the previous supply reaches a
programmed threshold voltage (See Figure 2). A
programmable sequence termination timer can be set
to disable all channels if the power-on sequence stalls.
During this mode, the HEALTHY# output remains
inactive and the RESET output remains active. When
the HEALTHY# output is true and RESET is false, that
signals the end of power-on sequencing mode.
Once the Power-on sequencing mode is complete, the
SMH4046 enters monitor control mode. Once all
supplies have sequenced on and the voltages are
above the UV settings, the Active DC Output Control
(ADOC), if enabled, brings the three DC-DC converter
supply output voltages to their programmed nominal
settings and adjusts the output voltage under all load
conditions. This feature is especially useful for
supplies without sense lines as the monitor VMx pins
can be routed and sense variations at the load. Typical
converters have
±2
to
±5%
accuracy output voltage
ratings. The Active DC Output Control feature of the
SMH4046 increases the accuracy to
±0.5%.
Summit Microelectronics, Inc
2082 1.7 08/23/04
2
SMH4046
Preliminary Information
GENERAL DESCRIPTION (CONTINUED)
The device also triggers outputs by monitoring fault
conditions.
The 10-bit ADC cycles through all
channels every 2 ms and checks the conversions
against the programmed threshold limits. The results
can be used to trigger the RESET, HEALTHY# and
FAULT outputs as well as to trigger a power-off or a
force- shutdown operation.
While the SMH4046 is in monitoring mode, a serial
interface command to margin the supply voltages can
bring the part into margining mode. In margining mode
the SMH4046 can margin the three supply voltages in
any combination of nominal, high or low voltage
settings using the ADOC feature, all to within ±0.5%.
The margin high and margin low voltage settings can
range from 0.9V to the overvoltage limit of the DC-DC
converters and depends on the margin range of the
converters. During this mode the HEALTHY# output is
always active and the RESET output is always inactive
regardless of the voltage threshold limit settings and
triggers. Furthermore, the triggers for power-off and
force-shutdown are temporarily disabled.
The power-off sequencing mode can only be entered
while the SMH4046 is in the monitoring mode. It can
be initiated by either bringing the HST_PWR pin
inactive, through the serial interface control, or
triggered by a channel exceeding its programmed
thresholds. Once power-off is initiated, active DC
control is disabled, and the PUP outputs are
sequenced off in either the same or reverse order as
power-on sequencing. Monitoring of the supply
voltages continues to ensure cascading of the supplies
as they turn off. The sequence termination timer can
be programmed to immediately disable all channels if
the power-off sequencing stalls. The RESET output
remains active throughout this mode while the
HEALTHY# output remains inactive.
The CARD_3V and CARD_5V monitor pins are also
used to detect overcurrents on the card side 3V and
5V supply. The FAULT pin is a programmable active
high/low open drain fault output that is asserted by the
SMH4046 when a programmed fault condition occurs
on the internal/external temperature sensor. If
programmed to do so, FAULT is asserted whenever
an over-current condition is detected. Fault will be
released at the same time that the VGATE outputs are
turned back on after a reset from the host on the
HST_PWR pin. Programming is accomplished by
using the I
2
C serial bus interface.
Summit Microelectronics, Inc
2082 1.7 08/23/04
3
SMH4046
Preliminary Information
INTERNAL FUNCTIONAL BLOCK DIAGRAM
VGG_CAP
V C C 12 V C C 5 V C C 3
1V R E F
H S T_
PW R
P D N 2# P D N 1#
H S T_
R S T#
FS
E X T_TE M P
VM
A
AD C _C AP
A
VM
B
AD C _C AP
B
VM
C
AD C _C AP
C
C AR D _3V
C AR D _5V
C AR D _12V
PUP
A
Intern al
Supp ly
VR EF
C o ntrol Lo gic
PUP
B
U VL O
10-B it
AD C
C ascade
Sequ en ce
C o ntro l
PUP
C
V G ATE 3
V G ATE 5
Tem p eratu re
Sensor
DRVREN#
H E ALTH Y#
IR Q
O utpu t
C o ntro l
RESET
C AR D _V _V LD
TR IM
A
TR IM _C AP
A
FAU LT
FP G A_N S TS
TR IM
B
TR IM _C AP
B
TR IM
C
TR IM _C AP
C
FILTE R _C AP
GND
FP G A_C G FD O N E
FP G A_N C FG
FP G A_D O
FP G A_D C LK
A2
SCL
SDA
Active
DC
O u tpu t
C o ntrol
I/O Interface,
E EP R O M M em o ry
an d L im it R eg isters
Figure 3 – Internal Functional Block Diagram
Summit Microelectronics, Inc
2082 1.7 08/23/04
4
SMH4046
Preliminary Information
PIN DESCRIPTIONS
Symbol
SCL
A2
HST_RST
Pin
1
2
3
Type
I
I
I
The I
2
C serial bus clock.
An external address bit for I
2
C.
Host reset. This input is the reset signal from the host interface. Asserting this
pin causes a reset sequence to be performed on the card. Programmable
polarity.
Host power-up enable. This input provides the host system with active control
over the sequencing of the power up operation. When de-asserted, the
SMH4046 holds the add-in card in reset and blocks all power to the back-end
logic. When HST_PWR is asserted, the power sequencing begins immediately
and the reset output is driven active after the time tPURST. Programmable
polarity.
Force Shutdown. This programmable active high/low input is used to
immediately turn off all converter enable signals and external FETs.
This input can be used to sense a voltage generated from an external
temperature monitoring device.
Active low Interrupt output. Generated by the SMH4046 on an error condition.
This signal can be used by external logic to interrupt the host.
RESET is a programmable active high/low open drain output that is asserted
by the SMH4046 when a programmed reset condition occurs.
FAULT is a programmable active high/low open drain fault output that is
asserted by the SMH4046 when a programmed fault condition occurs.
Healthy is a programmable active high/low open drain output that is asserted
by the SMH4046 when all programmed healthy conditions are met.
Ground.
Pin detect 1 is an active low CMOS level input. In conjunction with PND2#,
this signal indicates proper card insertion when taken low. This pin must be
connected to ground on the host side of the connector. PND1# and PND2#
should be placed on opposite corners of the connector and will preferably be
staggered shorter than the power connector pins. Board insertion is assumed
when PND1# and PND2# are low.
Pin detect 2 is an active low CMOS level input. In conjunction with PND1#,
this signal indicates proper card insertion when taken low. This pin must be
connected to ground on the host side of the connector. PND1# and PND2#
should be placed on opposite corners of the connector and will preferably be
staggered shorter than the power connector pins. Board insertion is assumed
when PND1# and PND2# are low.
Card voltage valid. This open drain output indicates that the card side voltages
are at or above their respective trip levels. Active high.
Positive converter sense line for DC/DC converter A
Output voltage used to control the output of DC/DC converter A.
External sample and hold capacitor input used to set the voltage on the
TRIMA pin.
Description
HST_PWR
4
I
FS
EXT_TEMP
IRQ#
RESET (RST)
FAULT
HEALTHY
GND
5
6
7
8
9
10
11
I
I
O
O
O
O
PWR
PND1#
12
I
PND2#
13
I
CARD_V_VLD
VMA
TRIMA
TRIM_CAPA
14
15
16
17
O
I
O
I
Summit Microelectronics, Inc
2082 1.7 08/23/04
5
Analog electronics
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