[AK4420]
AK4420
192kHz 24-Bit Stereo
ΔΣ
DAC with 2Vrms Output
GENERAL DESCRIPTION
The AK4420 is a 5V 24-bit stereo DAC with an integrated 2Vrms output buffer. A charge pump in the
buffer develops an internal negative power supply rail that enables a ground-referenced 2Vrms output.
Using AKM’s multi bit modulator architecture, the AK4420 delivers a wide dynamic range while preserving
linearity for improved THD+N performance. The AK4420 integrates a combination of switched-capacitor
and continuous-time filters, increasing performance for systems with excessive clock jitter. The 24-bit
word length and 192kHz sampling rate make this part ideal for a wide range of consumer audio
applications, such as DVD, AV receiver system and set-top boxes. The AK4420 is offered in a space
saving 16pin TSSOP package.
FEATURES
Sampling Rate Ranging from 8kHz to 192kHz
128 times Oversampling (Normal Speed Mode)
64 times Oversampling (Double Speed Mode)
32 times Oversampling (Quad Speed Mode)
24-Bit 8 times FIR Digital Filter
Switched-Capacitor Filter with High Tolerance to Clock Jitter
Single Ended 2Vrms Output Buffer
Soft mute
I/F format: 24-Bit MSB justified or I
2
S
Master clock: 512fs, 768fs or 1152fs (Normal Speed Mode)
256fs or 384fs (Double Speed Mode)
128fs, 192fs (Quad Speed Mode)
THD+N: -92dB
Dynamic Range: 105dB
Automatic Power-on Reset Circuit
Power supply: +4.5
∼
+5.5V
Ta = -20 to 85°C (ET), -40 to 85°C (VT)
Small Package: 16pin TSSOP (6.4mm x 5.0mm)
MCLK
VDD
DZF
VSS1
SMUTE
DIF
Control
Interface
Clock
Divider
ΔΣ
Modulator
ΔΣ
Modulator
LRCK
BICK
SDTI
Audio
Data
Interface
8X
Interpolator
8X
Interpolator
Charge
Pump
CP
1μ
CN
SCF
LPF
SCF
LPF
AOUTL
AOUTR
VEE
1μ
VSS2
CVDD
MS0683-E-06
-1-
2010/06
[AK4420]
■
Ordering Guide
AK4420ET
AK4420VT
AKD4420
-20
∼
+85°C
16pin TSSOP (0.65mm pitch)
-40
∼
+85°C
16pin TSSOP (0.65mm pitch)
Evaluation Board for AK4420
■
Pin Layout
CN
CP
SMUTE
MCLK
BICK
SDTI
LRCK
DIF
1
2
3
4
5
6
7
8
16
15
14
VEE
VSS2
CVDD
DZF
VSS1
VDD
AOUTL
AOUTR
AK4420
Top
View
13
12
11
10
9
Compatibility with AK4421 and AK4424
AK4420
-
24-bit MSB justified
I²S
SMUTE
DIF
+4.5
∼
+5.5V
-92dB
105dB
ET: -20
∼
+85°C
VT: -40
∼
+85°C
AK4421
-
24-bit MSB justified
I²S
SMUTE
DIF
+3.0
∼
+3.6V
-92dB (-3dBFS)
102dB
ET: -20
∼
+85°C
AK4424
X
I²S
DEM
SMUTE
+4.5
∼
+5.5V
-92dB
105dB
ET: -20
∼
+85°C
-: Not available
X: Available
Digital de-emphasis
I/F format
Pin out
Power Supply
THD+N
DR
Operating Temperature
Pin#3
Pin#8
MS0683-E-06
-2-
2010/06
[AK4420]
PIN/FUNCTION
No.
Pin Name
I/O
Function
Negative Charge Pump Capacitor Terminal Pin
Connect to CP with a 1.0μF capacitor that should have the low ESR
(Equivalent
Series Resistance)
over all temperature range. When this
capacitor has the polarity, the positive polarity pin should be connected to the
CP pin. Non polarity capacitors can also be used.
Positive Charge Pump Capacitor Terminal Pin
Connect to CN with a 1.0μF capacitor that should have the low ESR
(Equivalent
Series Resistance)
over all temperature range. When this
capacitor has the polarity, the positive polarity pin should be connected to the
CP pin. Non polarity capacitors can also be used.
Soft Mute Enable Pin (Internal pull down: 100kΩ)
“H”: Enable, “L”: Disable
Master Clock Input Pin
An external TTL clock should be input on this pin.
Audio Serial Data Clock Pin
Audio Serial Data Input Pin
L/R Clock Pin
Audio Data Interface Format Pin
“L”: Left Justified, “H”: I2S
Rch Analog Output Pin
When power down, outputs VSS(0V, typ).
Lch Analog Output Pin
When power down, outputs VSS(0V, typ).
DAC Power Supply Pin: 4.5V∼5.5V
Ground Pin1
1
CN
I
2
CP
I
3
4
5
6
7
8
9
10
11
12
13
14
15
SMUTE
MCLK
BICK
SDTI
LRCK
DIF
AOUTR
AOUTL
VDD
VSS1
DZF
CVDD
VSS2
I
I
I
I
I
I
O
O
-
-
O
-
-
Zero Input Detect Pin
Charge Pump Power Supply Pin: 4.5V∼5.5V
Ground Pin2
Negative Voltage Output Pin
Connect to VSS2 with a 1.0μF capacitor that should have the low ESR
16
(Equivalent
Series Resistance)
over all temperature range. When this
VEE
O
capacitor has the polarity, the positive polarity pin should be connected to the
VSS2 pin. Non polarity capacitors can also be used.
Note: All input pins except for the CN pin should not be left floating.
MS0683-E-06
-3-
2010/06
[AK4420]
ABSOLUTE MAXIMUM RATINGS
(VSS1=VSS2=0V;
Note 1)
Parameter
Power Supply
Symbol
VDD
CVDD
IIN
VIND
Ta
Ta
Tstg
min
-0.3
-0.3
-
-0.3
-20
-40
-65
max
+6.0
+6.0
±10
VDD+0.3
85
85
150
Units
V
V
mA
V
°C
°C
°C
Input Current (any pins except for supplies)
Input Voltage
Ambient Operating Temperature AK4420ET
AK4420VT
Storage Temperature
Note 1. All voltages with respect to ground.
Note 2. VSS1, VSS2 connect to the same analog grand.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS1=VSS2=0V;
Note 1)
Parameter
Power Supply
Note 3. CVDD should be equal to VDD
*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
Symbol
VDD
CVDD
min
+4.5
typ
+5.0
VDD
max
+5.5
Units
V
MS0683-E-06
-4-
2010/06
[AK4420]
ANALOG CHARACTERISTICS
(Ta = 25°C; VDD=CVDD = +5.0V; fs = 44.1 kHz; BICK = 64fs; Signal Frequency = 1 kHz;
24bit Input Data; Measurement frequency = 20Hz
∼
20kHz; R
L
≥5kΩ)
Parameter
min
typ
max
Resolution
24
Dynamic Characteristics
(Note
4)
THD+N (0dBFS)
fs=44.1kHz, BW=20kHz
-92
-84
fs=96kHz, BW=40kHz
-92
-
fs=192kHz, BW=40kHz
-92
-
Dynamic Range (-60dBFS with A-weighted. (Note
5)
98
105
S/N (A-weighted. (Note
6)
98
105
Interchannel Isolation (1kHz)
90
100
Interchannel Gain Mismatch
0.2
0.5
DC Accuracy
DC Offset
(at output pin)
-60
0
+60
Gain Drift
100
-
Output Voltage (Note
7)
1.97
2.12
2.27
Load Capacitance (Note
8)
25
Load Resistance
5
Power Supplies
Power Supply Current: (Note
9)
24
36
Normal Operation (fs≤96kHz)
27
40
Normal Operation (fs=192kHz)
10
100
Power-Down Mode (Note
10)
Note 4. Measured by Audio Precision (System Two). Refer to the evaluation board manual.
Note 5. 98dB for 16bit input data
Note 6. S/N does not depend on input data size.
Note 7. Full-scale voltage (0dB). Output voltage is proportional to the voltage of VDD,
AOUT (typ.@0dB) = 2.12Vrms × VDD/5.
Note 8. In case of driving capacitive load, inset a resistor between the output pin and the capacitive load.
Note 9. The current into VDD and CVDD.
Note 10. All digital inputs including clock pins (MCLK, BICK and LRCK) are fixed to VSS or VDD
Units
Bits
dB
dB
dB
dB
dB
dB
dB
mV
ppm/°C
Vrms
pF
kΩ
mA
mA
μA
MS0683-E-06
-5-
2010/06
PCB Design
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