530EB327M000DG datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > oscillator> 530EB327M000DG

530EB327M000DG: DescriptionLVPECL Output Clock Oscillator, 327MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; Categoryoscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

530EB327M000DG Overview

LVPECL Output Clock Oscillator, 327MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

530EB327M000DG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
package instruction	ROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Code	unknown
Is Samacsys	N
Other features	TRAY
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	20%
JESD-609 code	e4
Manufacturer's serial number	530
Installation features	SURFACE MOUNT
Nominal operating frequency	327 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVPECL
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	2.75 V
Minimum supply voltage	2.25 V
Nominal supply voltage	2.5 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)
Base Number Matches	1

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

A circuit diagram of a household inverter power supply with excellent performance

Fuse melt blown alarm relay circuit

Three-phase asynchronous motor atypical control circuit_1

Temperature sensor and digital voltmeter interface

Four types of grating circuits using integrated circuits

Computer motherboard circuit diagram 815 4_36

On the selection of embedded LINUX development environment: I am a newbie and want to develop network communication products in LINUX environment. Can you please tell me which development environment is better? Where can I get it? Thanks a lot!!!...; kk02157882 Linux and Android

DSP28335 timer and external input interrupt: [p=26, null, left][color=#333333][font=Arial]External interrupt initialization[/font][/color][/p][p=26, null, left][color=#333333][font=Arial]#include "extint.h"[/font][/color][/p][p=26, null, left][c...; bood123 Microcontroller MCU

LM3S618+TFT: LM3S618+TFT module test board The chip in the red frame is LM3S618 The green board is the TFT module[[i]This post was last edited by deweyled on 2011-6-29 21:00[/i]]...; deweyled Microcontroller MCU

Zhou Ligong's EDA Experiment and Practice: Zhou Ligong's EDA Experiment and Practice is an absolutely rare and good material. The electronic version is difficult to find online. Content introduction: This book introduces EDA technology and rel...; 白丁 FPGA/CPLD

Unforgettable 2017-a busy and confusing year: 2017 was a rather tangled and busy year, with several major things throughout: internship, thesis, work, and training. This year, I experienced the whole process of switching from an EE engineer to a ...; 人民币的幻想 Talking

Infrared remote control information and production: Share some information about infrared remote control and production. I spent a long time searching online to organize and download the information....; lonely_boy RF/Wirelessly

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components