STM6720TGWB6F datasheet, PDF - EEWORLD Datasheet

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STM6720TGWB6F: DescriptionSupervisory Circuits Dual/Triple Ultra- Low Voltage Super.; CategoryPower/power management The power supply circuit; File Size594KB，30 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/

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STM6720TGWB6F Overview

Supervisory Circuits Dual/Triple Ultra- Low Voltage Super.

STM6720TGWB6F Parametric

Parameter Name	Attribute value
Brand Name	STMicroelectronics
Maker	STMicroelectronics
Parts packaging code	SOIC
package instruction	LSSOP, TSOP6,.11,37
Contacts	6
Reach Compliance Code	compliant
ECCN code	EAR99
Factory Lead Time	18 weeks
Other features	RESET THRESHOLD VOLTAGES ARE 3.075V AND 1.110V; MANUAL RESET INPUT
Adjustable threshold	YES
Analog Integrated Circuits - Other Types	POWER SUPPLY SUPPORT CIRCUIT
JESD-30 code	R-PDSO-G6
JESD-609 code	e4
length	2.9 mm
Humidity sensitivity level	1
Number of channels	1
Number of functions	1
Number of terminals	6
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	LSSOP
Encapsulate equivalent code	TSOP6,.11,37
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, LOW PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260
power supply	0.8/5.5 V
Certification status	Not Qualified
Maximum seat height	1.45 mm
Maximum supply current (Isup)	0.035 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	0.8 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING
Terminal pitch	0.95 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	1.6 mm
Base Number Matches	1

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STM6717/6718/6719/6720

STM6777/6778/6779/6780

Dual/triple ultra-low voltage supervisors

with push-button reset (with delay option)

Features

■

Primary supply (V

CC1

) monitor.

Fixed (factory-programmed) reset thresholds:

4.63 V to 1.58 V

Secondary supply (V

CC2

) monitor

(STM6717/18/19/20/77/78)

Fixed (factory-programmed) reset thresholds:

3.08 V to 0.79 V

Tertiary supply monitor (using externally

adjustable RSTIN): 0.626 V internal reference

RST outputs (push-pull or open drain); state

guaranteed if V

CC1

or V

CC2

≥

0.8 V

Reset delay time (t

rec

) on power-up: 13.2 ms,

210 ms, 900 ms (typ)

Manual reset input (MR)

Optional delayed manual reset input (MRC)

with external capacitor (STM6777/78/79/80)

Low supply current - 11 µA (typ),

CC1

= V

CC2

= 3.6 V

Operating temperature: –40 °C to 85 °C

(industrial grade)

Device summary

Monitored voltages

Part

number

STM6717

STM6718

STM6719

STM6720

STM6777

STM6778

STM6779

STM6780

CC1

✔

CC2

✔

RSTIN

Manual reset Delayed MR

input (MR)

pin (MRC)

✔

Reset output (RST)

Active-low

(push-pull)

Active-low

(open drain)

✔

Package

SOT23-5 (WY)

■

SOT23-6 (WB)

Table 1.

August 2011

Doc ID 11469 Rev 8

1/30

www.st.com

List of figures

STM6717/6718/6719/6720/STM6777/6778/6779/6780

List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

Figure 10.

Figure 11.

Figure 12.

Figure 13.

Figure 14.

Figure 15.

Figure 16.

Figure 17.

Figure 18.

Figure 19.

Figure 20.

Figure 21.

Figure 22.

Figure 23.

Figure 24.

Figure 25.

Figure 26.

Figure 27.

Figure 28.

Figure 29.

Figure 30.

Logic diagram (STM6717/18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Logic diagram (STM6777/78) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Logic diagram (STM6719/20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Logic diagram (STM6779/80) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

STM6717/18 SOT23-5 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

STM6777/78 SOT23-6 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

STM6719/20 SOT23-6 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

STM6779/80 SOT23-6 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

STM67xx interface to processor with bi-directional reset pins . . . . . . . . . . . . . . . . . . . . . . 10

Ensuring RST valid to V

= 0 (active-low, push-pull outputs). . . . . . . . . . . . . . . . . . . . . . 10

Supply current vs. temperature (V

CC1

= 5.5 V; V

CC2

= 3.6 V) . . . . . . . . . . . . . . . . . . . . . . 11

Supply current vs. temperature (V

CC1

= 3.6 V; V

CC2

= 2.75 V) . . . . . . . . . . . . . . . . . . . . . 11

Supply current vs. temperature (V

CC1

= 3.0 V; V

CC2

= 2.0 V) . . . . . . . . . . . . . . . . . . . . . . 12

Supply current vs. temperature (V

CC1

= 2.0 V; V

CC2

= 1.0 V) . . . . . . . . . . . . . . . . . . . . . . 12

Normalized V

reset time-out period vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Maximum V

transient duration vs. reset threshold overdrive . . . . . . . . . . . . . . . . . . . . . 13

Normalized V

RST1

threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Normalized V

RST2

threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Reset input threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

CC1

-to-reset delay vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Reset input-to-reset output delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

MR-to-reset output delay vs. temperature (V

CC1

= 3.6V) . . . . . . . . . . . . . . . . . . . . . . . . . . 16

AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

MR timing waveform (STM6717/18/19/20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

MR timing waveform (STM6777/78/79/80) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

SOT23-5 – 5-lead small outline transistor package mechanical drawing . . . . . . . . . . . . . . 23

SOT23-6 – 6-lead small outline transistor package mechanical drawing . . . . . . . . . . . . . . 24

Carrier tape for SOT23-5L and SOT23-6L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4/30

Doc ID 11469 Rev 8

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