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70V3319S166BCG

Description
CABGA-256, Tray
Categorystorage   
File Size459KB,24 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance  
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70V3319S166BCG Overview

CABGA-256, Tray

70V3319S166BCG Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeCABGA
package instructionLBGA, BGA256,16X16,40
Contacts256
Manufacturer packaging codeBCG256
Reach Compliance Codecompliant
ECCN code3A991.B.2.A
Samacsys Confidence3
Samacsys StatusReleased
Samacsys PartID11322602
Samacsys Pin Count256
Samacsys Part CategoryIntegrated Circuit
Samacsys Package CategoryBGA
Samacsys Footprint NameBC256-_-
Samacsys Released Date2020-02-19 16:27:07
Is SamacsysN
Maximum access time3.6 ns
Other featuresFLOW-THROUGH OR PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)166 MHz
I/O typeCOMMON
JESD-30 codeS-CBGA-B256
JESD-609 codee1
length17 mm
memory density4718592 bit
Memory IC TypeDUAL-PORT SRAM
memory width18
Humidity sensitivity level3
Number of functions1
Number of ports2
Number of terminals256
word count262144 words
character code256000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize256KX18
Output characteristics3-STATE
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeLBGA
Encapsulate equivalent codeBGA256,16X16,40
Package shapeSQUARE
Package formGRID ARRAY, LOW PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)260
power supply2.5/3.3,3.3 V
Certification statusNot Qualified
Maximum seat height1.7 mm
Maximum standby current0.03 A
Minimum standby current3.15 V
Maximum slew rate0.5 mA
Maximum supply voltage (Vsup)3.45 V
Minimum supply voltage (Vsup)3.15 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Silver/Copper (Sn/Ag/Cu)
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperature30
width17 mm
Base Number Matches1
HIGH-SPEED 3.3V
70V3319/99S
256/128K x 18
SYNCHRONOUS
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
Features:
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed data access
– Commercial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
– Industrial: 4.2ns (133MHz) (max.)
Selectable Pipelined or Flow-Through output mode
– Due to limited pin count PL/
FT
option is not supported
on the 128-pin TQFP package. Device is pipelined
outputs only on each port.
Counter enable and repeat features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 6ns cycle time, 166MHz operation (6Gbps bandwidth)
– Fast 3.6ns clock to data out
– 1.7ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 166MHz
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
Separate byte controls for multiplexed bus and bus
matching compatibility
Dual Cycle Deselect (DCD) for Pipelined Output mode
LVTTL- compatible, single 3.3V (±150mV) power supply
for core
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port
Industrial temperature range (-40°C to +85°C) is
available at 133MHz.
Available in a 128-pin Thin Quad Flatpack, 208-pin fine
pitch Ball Grid Array, and 256-pin Ball
Grid Array
Supports JTAG features compliant to IEEE 1149.1
– Due to limited pin count, JTAG is not supported on the
128-pin TQFP package
Green parts available, see ordering information
Functional Block Diagram
UB
L
LB
L
UB
R
LB
R
FT/PIPE
L
1/0
0a 1a
a
0b 1b
b
1b 0b
b
1a 0a
a
1/0
FT/PIPE
R
R/W
L
CE
0L
CE
1L
1
0
1/0
B
W
0
L
B
W
1
L
B B
WW
1 0
R R
1
0
1/0
R/W
R
CE
0R
CE
1R
OE
L
Dout0-8_L
Dout9-17_L
Dout0-8_R
Dout9-17_R
OE
R
1b 0b 1a 0a
0a 1a 0b 1b
0/1
,
FT/PIPE
R
FT/PIPE
L
0/1
ab
ba
256K x 18
MEMORY
ARRAY
I/O
0L
- I/O
17L
Din_L
Din_R
I/O
0R
- I/O
17R
CLK
L
A
17L(1)
A
0L
REPEAT
L
ADS
L
CNTEN
L
CLK
R
,
A
17R(1)
Counter/
Address
Reg.
ADDR_L
ADDR_R
Counter/
Address
Reg.
A
0R
REPEAT
R
ADS
R
CNTEN
R
5623 tbl 01
NOTE:
1. A
17
is a NC for IDT70V3399.
TDI
JTAG
TDO
TCK
TMS
TRST
NOVEMBER 2019
DSC
5623/13
1
©2019 Integrated Device Technology, Inc.
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