A Product Line of
Diodes Incorporated
ZNBG4003
4 STAGE LNA BIAS CONTROLLER
Description
The ZNBG4003 is a four stage depletion mode FET bias controller
intended primarily for satellite Low Noise Block’s (LNB’s), but its also
suitable for other LNA applications such as those in found in PMR’s
and microwave links. The ZNBG4003 provides each FET with a
Pin Assignments
NEW PRODUCT
negative gate voltage and positive drain voltage with user
programmable drain current.
Features
•
•
•
•
•
•
•
•
•
•
•
Four stage FET bias controller
Operating range of 4.75V to 8.0V
FET drain voltages set at 2.0V
FET drain current selectable from 0 to 15mA
Allows first and second stage FETs to be run at different
(optimum) drain currents
FET drain voltages and currents stable over temperature
FETs protected against overstress during power-up and power-
down.
Internal negative supply generator allowing single supply
operation (available for external use)
Low external component count
Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)
Halogen and Antimony Free. “Green” Device (Note 3)
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•
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Notes:
Top view
Bottom view
Applications
Two single type Twin LNB’s
Twin LNB’s
Quad LNB’s
Microwave links
PMR and Cellular telephone systems
1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant.
2. See http://www.diodes.com for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green" and Lead-free.
3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and
<1000ppm antimony compounds.
Twin Universal LNB System Diagram
ZNBG4003
Document number: DS35007 Rev. 1 - 2
1 of 6
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June 2012
© Diodes Incorporated
A Product Line of
Diodes Incorporated
ZNBG4003
Device Description
The ZNBG series of devices are designed to meet the bias
requirements of GaAs and HEMT FETs commonly used in
satellite receiver LNBs with a minimum of external components.
The ZNBG4003 provides four FET bias stages, arranged in two
pairs of two. Resistors connected to pins R
CAL
1 and R
CAL
2 set the
recommended gate and drain capacitors. These ensure RF
stability and minimal injected noise.
It is possible to use less than the devices full complement of FET
bias controls, unused drain and gate connections can be left open
circuit without affecting operation of the remaining bias circuits.
To protect the external FETs the circuits have been designed to
ensure that, under any conditions including power up/down
transients, the gate drive from the bias circuits cannot exceed -3V.
Additionally each stage has its own individual current limiter.
Furthermore if the negative rail experiences a fault condition, such
as overload or short circuit, the drain supply to the FETs will shut
down avoiding excessive current flow.
To minimise PCB space ZNBG4003 is packaged in the 16 pin
3mm x 3mm QFN package.
Device operating temperature is -40°C to +85°C to suit a wide
range of environmental conditions.
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FET drain currents of each pair over the range of 0 to 15mA,
allowing input FETs to be biased for optimum noise and amplifier
FETs for optimum gain.
Drain voltages of all stages are set at 2.0V. The drain supplies are
current limited to approximately 5% above the operating currents
set by the Rcal resistors.
Depletion mode FETs require a negative voltage bias supply when
operated in grounded source circuits. The ZNBG4003 includes an
integrated switched capacitor DC-DC converter generating a
regulated output of -2.5V to allow single supply operation.
These devices are unconditionally stable over the full working
temperature with the FETs in place, subject to the inclusion of the
Typical Application Circuit
ZNBG4003
Document number: DS35007 Rev. 1 - 2
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June 2012
© Diodes Incorporated
A Product Line of
Diodes Incorporated
ZNBG4003
Absolute Maximum Ratings
(@T
A
= +25°C, unless otherwise specified.)
Parameter
Supply Voltage
Supply Current
Power Dissipation
(Note 5)
Rating
-0.6 to +10
80
500
-40 to +85
-40 to +150
Unit
V
mA
mW
°C
°C
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Opereating Temperature Range
Storage Temerature Range
Electrical Characteristics
(@ T
AMB
= +25°C, V
CC
= 5.0V (Note 1), R
CAL
1 = R
CAL
2 = 39k (setting I
D
to 10mA) unless otherwise specified.)
Symbol
V
CC
I
CC
I
CC(L)
V
CSUB
V
CSUB(L)
F
OSC
Parameter
Operating Voltage Range (Note 4)
Supply Current
Substrate Voltage (Note 6,7)
Oscillator Frequency
Conditions
I
D1
= I
D2
= I
D3
= I
D4
= 0
I
D1
= I
D2
= I
D3
= I
D4
= 10mA
I
CSUB
= 0
I
CSUB
= -100µA
Min
4.75
Typ
1.8
43
Max
8.0
4.5
45
-2.0
-1.9
600
Unit
V
mA
V
V
kHz
-3.0
150
-2.65
-2.55
240
Gate Characteristics
Gate (G1 to G4)
I
G
V
G(L)
V
G(H)
Current Range
Voltage Low
Voltage High
I
D
= 12mA, I
G
= 10µA
I
D
= 8mA, I
G
= 0
-100
-3.0
0
-2.5
0.7
+500
-2.0
1.0
µA
V
V
Drain Characteristics
Drain (D1 to D4)
I
D
I
D(OP)
V
D(OP)
dI
D
/dV
CC
dI
D
/d
TOP
dI
D
/dV
CC
dI
D
/d
TOP
Current Range
Current Operating
Voltage Operating
Δ
I
D
vs V
CC
Δ
I
D
vs T
OP
Δ
V
D
vs V
CC
Δ
V
D
vs T
OP
Standard Application Circuit
I
D
= 10mA
V
CC
= 5.0V to 8.0V
T
OP
= -40°C to +85°C
V
CC
= 5.0V to 8.0V
T
OP
= -40°C to +85°C
C
GRATE-GND
= 10nF,
C
DRAIN-GND
= 10nF
C
GRATE-GND
= 10nF,
C
DRAIN-GND
= 10nF
0
8
1.8
10
2.0
1.2
0.09
0.08
110
15
12.5
2.2
mA
mA
V
%/V
%/°C
%/V
ppm/°C
Output Noise
(Note 8)
V
D(NOISE)
V
G(NOISE)
Notes:
Drain Voltage
Gate Voltage
0.02
0.005
Vpk-pk
Vpk-pk
4. The two V
CC
pins are internally connected, only one of the pins needs to be powered for the device to function. See applications section for further
information.
5. ESD sensitive, handling precautions are recommended.
6. The negative bias voltages are generated on-chip using an internal oscillator. Two external capacitors, C
NB
and C
SUB
of value 47nF are required for this
purpose.
7. The package (QFN1633) exposed pad must either be connected to Csub or left open circuit.
8. Noise voltage measurements are made with FETs and gate and drain capacitors of value 10nF in place. Noise voltages are not measured in production.
ZNBG4003
Document number: DS35007 Rev. 1 - 2
3 of 6
www.diodes.com
June 2012
© Diodes Incorporated
A Product Line of
Diodes Incorporated
ZNBG4003
Typical Characteristics
(measured @ T
AMB
= +25°C, V
CC
= 5.0V)
15
DRAIN CURRENT (mA)
10
NEW PRODUCT
5
0
10
100
R
CAL
Drain Current vs. R
CAL
1000
Application Information
Above is a partial applications circuit for the ZNBG4003 showing
all external components needed for biasing one of the four FET
stages available. Each bias stage is provided with a gate and
drain pin. The drain pin provides a regulated 2.0V supply that
includes a drain current monitor. The drain current taken by the
external FET is compared with a user selected level, generating a
signal that adjusts the gate voltage of the FET to obtain the
required drain current. If for any reason, an attempt is made to
draw more than the user set drain current from the drain pin, the
drain voltage will be reduced to ensure excess current is not
taken. The gate pin drivers are also current limited.
The bias stages are split up into two pairs, with the drain current of
each pair set by an external R
CAL
resistor. R
CAL
1 sets the drain
currents of stages 1 and 3, whilst R
CAL
2 sets the drain currents of
stages 2 and 4. This allows the optimisation of drain currents for
differing tasks such as input stages where noise can be critical
and later amplifier stages where gain may be more important.
A graph showing the relationship between the value of R
CAL
and I
D
is provided in the Typical Characteristics section of this datasheet.
If any bias stages are not required, their gate and drain pins may
be left open circuit. If all bias stages associated with an R
CAL
resistor are not required, then this resistor may be omitted.
To ease PCB layout, the pinout for the ZNBG4003 includes two
V
CC
pins. These pins are internally connected so only one of the
pins needs to be powered for the device to function. It is probable
that the extra pin will help avoid the need for trace cross-over
components or ground plane disruption from reverse side PCB
links. Note that the exposed pad of the package must be either left
floating or connected to C
SUB
.
The ZNBG4003 includes a switched capacitor DC-DC converter
that is used to generate the negative supply required to bias
depletion mode FETs used in common source circuit configuration
as shown above. This converter uses two external capacitors, C
NB
the charge transfer capacitor and C
SUB
the output reservoir
capacitor. The circuit provides a regulated -2.5V supply both for
gate driver use and for external use if required (for extra discrete
bias stages, mixer bias, local oscillator bias etc.). The -2.5V
supply is available from the C
SUB
pin.
ZNBG4003
Document number: DS35007 Rev. 1 - 2
4 of 6
www.diodes.com
June 2012
© Diodes Incorporated
A Product Line of
Diodes Incorporated
ZNBG4003
Ordering Information
13” Tape & Reel
Quantity
3000/Tape & Reel
Part Number
ZNBG4003JA16TC
Packaging
QFN1633
Part Number Suffix
TC
NEW PRODUCT
Marking Information
Pin 1
ZNBG
4003
YYWW
Part Name
Date Code
Year/Week
Package Outline Dimensions
(All dimensions in mm.)
QFN16 3x3
Dim
Min
Max
A
0.55
0.65
A1
0.00
0.05
A3
0.15 Typ
b
0.18
0.28
D
2.95
3.05
D2
1.40
1.60
e
0.50 BSC
E
2.95
3.05
E2
1.40
1.60
L
0.35
0.45
Z
0.625 Typ
All Dimensions in mm
ZNBG4003
Document number: DS35007 Rev. 1 - 2
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June 2012
© Diodes Incorporated
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