CMOS Static RAM
1 Meg (64K x 16-Bit)
Features
Description
IDT71016S
◆
◆
◆
◆
◆
◆
◆
64K x 16 advanced high-speed CMOS Static RAM
Equal access and cycle times
– Commercial : 12/15/20ns
– Industrial: 15/20ns
One Chip Select plus one Output Enable pin
Bidirectional data inputs and outputs directly TTL-
compatible
Low power consumption via chip deselect
Upper and Lower Byte Enable Pins
Commercial and industrial product available in 44-pin
Plastic SOJ package and 44-pin TSOP package
The IDT71016 is a 1,048,576-bit high-speed Static RAM organized
as 64K x 16. It is fabricated using high-perfomance, high-reliability CMOS
technology. This state-of-the-art technology, combined with innovative
circuit design techniques, provides a cost-effective solution for high-speed
memory needs.
The IDT71016 has an output enable pin which operates as fast as 7ns,
with address access times as fast as 12ns. All bidirectional inputs and
outputs of the IDT71016 are TTL-compatible and operation is from a single
5V supply. Fully static asynchronous circuitry is used, requiring no clocks
or refresh for operation.
The IDT71016 is packaged in a JEDEC standard 44-pin Plastic SOJ
and 44-pin TSOP Type II.
Functional Block Diagram
OE
Output
Enable
Buffer
A0 - A15
Address
Buffers
Row / Column
Decoders
I/O 15
Chip
Enable
Buffer
Sense
Amps
and
Write
Drivers
8
Low
Byte
I/O
Buffer
8
8
High
Byte
I/O
Buffer
8
,
CS
I/O 8
WE
Write
Enable
Buffer
64K x 16
Memory
Array
16
I/O 7
I/O 0
BHE
Byte
Enable
Buffers
BLE
3210 drw 01
SEPTEMBER 2013
1
©2013 Integrated Device Technology, Inc.
DSC-3210/11
IDT71016, CMOS Static RAM
1 Meg (64K x 16-bit)
Commercial and Industrial Temperature Ranges
Pin Configurations
A4
A3
A2
A1
A0
CS
I/O 0
I/O 1
I/O 2
I/O 3
V
CC
V
SS
I/O 4
I/O 5
I/O 6
I/O 7
WE
A15
A14
A13
A12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
SO44-1
SO44-2
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BLE
I/O 15
I/O 14
I/O 13
I/O 12
V
SS
V
CC
I/O 11
I/O 10
I/O 9
I/O 8
NC
A8
A9
A10
A11
NC
3210 drw 02
Pin Descriptions
A
0
- A
15
CS
WE
OE
BHE
BLE
I/O
0
- I/O
15
V
CC
V
SS
Address Inputs
Chip Select
Write Enable
Output Enable
High Byte Enable
Low Byte Enable
Data Input/Output
5.0V Power
Ground
Input
Input
Input
Input
Input
Input
I/O
Pwr
Gnd
3210 tbl 01
,
SOJ/TSOP
Top View
Truth Table
(1)
CS
H
L
L
L
L
L
L
L
L
OE
X
L
L
L
X
X
X
H
X
WE
X
H
H
H
L
L
L
H
X
BLE
X
L
H
L
L
L
H
X
H
BHE
X
H
L
L
L
H
L
X
H
I/O
0
- I/O
7
High-Z
DATAOUT
High-Z
DATAOUT
DATAIN
DATAIN
High-Z
High-Z
High-Z
I/O
8
- I/O
15
High-Z
High-Z
DATAOUT
DATAOUT`
DATAIN
High-Z
DATAIN
High-Z
High-Z
Function
Deselected - Standby
Low Byte Read
High Byte Read
Word Read
Word Write
Low Byte Write
High Byte Write
Outputs Disabled
Outputs Disabled
3210 tbl 02
NOTE:
1. H = V
IH
, L = V
IL
, X = Don't care.
6.42
2
IDT71016, CMOS Static RAM
1 Meg (64K x 16-bit)
Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
T
BIAS
T
STG
P
T
I
OUT
Rating
Terminal Voltage with
Respect to GND
Temperature
Under Bias
Storage
Temperature
Power Dissipation
DC Output Current
Value
-0.5 to +7.0
-55 to +125
-55 to +125
1.25
50
Unit
V
o
Recommended Operating
Temperature and Supply Voltage
Grade
Commercial
Industrial
Temperature
0°C to +70°C
–40°C to +85°C
GND
0V
0V
V
CC
5.0V ± 10%
5.0V ± 10%
3210 tbl 04
C
C
o
Recommended DC Operating
Conditions
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
-0.5
(1)
Typ.
5.0
0
____
____
W
mA
3210 tbl 03
Max.
5.5
0
V
DD
+0.5
0.8
Unit
V
V
V
V
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. V
TERM
must not exceed V
CC
+ 0.5V.
3210 tbl 05
NOTE:
1. V
IL
(min.) = –1.5V for pulse width less than tRC/2, once per cycle.
Capacitance
Symbol
C
IN
C
I/O
(T
A
= +25° C, f = 1.0MHz, SOJ/TSOP Package)
Parameter
(1)
Input Capacitance
I/O Capacitance
Conditions
V
IN
= 3dV
V
OUT
= 3dV
Max.
6
7
Unit
pF
pF
DC Electrical Characteristics
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
3210 tbl 06
NOTE:
1. This parameter is guaranteed by device characterization, but not production
tested.
(V
CC
= 5.0V ± 10%, Commercial and Industrial Temperature Range)
Test Conditions
V
CC
= Max., V
IN
= GND to V
CC
V
CC
= Max.,
CS
= V
IH
, V
OUT
= GND to V
CC
I
OL
= 8mA, V
CC
= Min.
I
OH
= -4mA, V
CC
= Min.
Min.
___
___
___
Max.
5
5
0.4
___
Unit
µA
µA
V
V
3210 tbl 07
2.4
DC Electrical Characteristics
(1)
(V
CC
= 5.0V ± 10%, V
LC
= 0.2V, V
HC
= V
CC
–0.2V)
71016S12
Symbol
I
CC
I
SB
Parameter
Dynamic Operating Current
CS
< V
IL
, Outputs Open, V
CC
= Max., f = f
MAX
(2)
Standby Power Supply Current (TTL Level)
CS
> V
IH
, Outputs Open, V
CC
= Max., F = f
MAX
(2)
Standby Power Supply Current (CMOS Level)
CS
> V
HC
, Outputs Open, V
CC
= Max., f = 0
(2)
V
IN
< V
LC
or V
IN
> V
HC
Com'l.
210
60
10
71016S15
Com'l.
180
50
10
Ind.
180
50
10
71016S20
Com'l.
170
45
10
Ind.
170
45
10
Unit
mA
mA
mA
I
SB1
NOTES:
1. All values are maximum guaranteed values.
2. f
MAX
= 1/t
RC
(all address inputs are cycling at f
MAX
); f = 0 means no address input lines are changing .
3210 tbl 08
6.42
3
IDT71016, CMOS Static RAM
1 Meg (64K x 16-bit)
Commercial and Industrial Temperature Ranges
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
GND to 3.0V
1.5ns
1.5V
1.5V
See Figure 1, 2 and 3
3210 tbl 09
AC Test Loads
5V
480Ω
5V
480Ω
DATA
OUT
DATA
OUT
30pF*
255Ω
5pF*
255Ω
3210 drw 04
3210 drw 03
,
,
*Including jig and scope capacitance.
Figure 1. AC Test Load
Figure 2. AC Test Load
(for t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
OW,
and t
WHZ
)
7
Δt
AA,
t
ACS
(Typical, ns) 5
4
3
2
1
•
•
•
•
•
•
•
6
,
CAPACITANCE (pF)
3210 drw 05
8 20 40 60 80 100 120 140 160 180 200
Figure 3. Output Capacitive Derating
6.42
4
IDT71016, CMOS Static RAM
1 Meg (64K x 16-bit)
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
Symbol
READ CYCLE
t
RC
t
AA
t
ACS
t
CLZ
(1)
t
CHZ
(1)
t
OE
t
OLZ
(1)
t
OHZ
(1)
t
OH
t
BE
t
BLZ
(1)
t
BHZ
(1)
WRITE CYCLE
t
WC
t
AW
t
CW
t
BW
t
AS
t
WR
t
WP
t
DW
t
DH
t
OW
(1)
t
WHZ
(1)
Write Cycle Time
Address Valid to End of Write
Chip Select Low to End of Write
Byte Enable Low to End of Write
Address Set-up Time
Address Hold from End of Write
Write Pulse Width
Data Valid to End of Write
Data Hold Time
Write Enable High to Output in Low-Z
Write Enable Low to Output in High-Z
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select Low to Output in Low-Z
Chip Select High to Output in High-Z
Output Enable Low to Output Valid
Output Enable Low to Output in Low-Z
Output Enable High to Output in High-Z
Output Hold from Address Change
Byte Enable Low to Output Valid
Byte Enable Low to Output in Low-Z
Byte Enable High to Output in High-Z
Parameter
(
V
CC = 5.0V ± 10%, Commercial and Industrial Range
)
71016S12
(2)
Min.
Max.
71016S15
Min.
Max.
71016S20
Min.
Max.
Unit
12
____
____
____
15
____
____
____
20
____
____
____
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
12
12
____
15
15
____
20
20
____
4
____
5
____
5
____
6
7
____
6
8
____
8
10
____
____
____
____
0
____
0
____
0
____
6
____
6
____
8
____
4
____
4
____
5
____
7
____
8
____
10
____
0
____
0
____
0
____
6
6
8
12
9
9
9
0
0
9
7
0
1
____
____
____
____
____
____
____
____
____
____
____
15
10
10
10
0
0
10
8
0
1
____
____
____
____
____
____
____
____
____
____
____
20
12
12
12
0
0
12
10
0
1
____
____
____
____
____
____
____
____
____
____
____
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3210 tbl 10
6
6
8
NOTE:
1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
2. 12ns commercial only.
Timing Waveform of Read Cycle No. 1
(1,2,3)
t
RC
ADDRESS
t
AA
t
OH
DATA
OUT
PREVIOUS DATA
OUT
VALID
t
OH
DATA
OUT
VALID
3210 drw 06
NOTES:
1.
WE
is HIGH for Read Cycle.
2. Device is continuously selected,
CS
is LOW.
3.
OE, BHE,
and
BLE
are LOW.
,
6.42
5
Embedded System
京公网安备 11010802033920号
EEWORLD
