WM8918CGEFL/RV datasheet, PDF - EEWORLD Datasheet

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WM8918CGEFL/RV: DescriptionConsumer Circuit, CMOS, PQCC32, 4 X 4 MM, 0.75 MM HEIGHT, 0.40 MM PITCH, LEAD FREE, PLASTIC, QFN-32; CategoryOther integrated circuit (IC) Consumption circuit; File Size2MB，176 Pages; ManufacturerCirrus Logic; Websitehttp://www.cirrus.com; Environmental Compliance

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WM8918CGEFL/RV Overview

Consumer Circuit, CMOS, PQCC32, 4 X 4 MM, 0.75 MM HEIGHT, 0.40 MM PITCH, LEAD FREE, PLASTIC, QFN-32

WM8918CGEFL/RV Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Objectid	8077929122
package instruction	HVQCCN,
Reach Compliance Code	compliant
Other features	IT ALSO REQUIRES ANALOG SUPPLY RANGE 1.71 TO 2 VOLT
Commercial integrated circuit types	CONSUMER CIRCUIT
JESD-30 code	S-PQCC-N32
length	4 mm
Number of functions	1
Number of terminals	32
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	HVQCCN
Package shape	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Maximum seat height	0.8 mm
Maximum supply voltage (Vsup)	1.98 V
Minimum supply voltage (Vsup)	0.95 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	NO LEAD
Terminal pitch	0.4 mm
Terminal location	QUAD
width	4 mm

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DESCRIPTION

The WM8918 is a high performance ultra-low power stereo

DAC optimised for portable audio applications.

The device features stereo ground-referenced headphone

amplifiers using the Wolfson ‘Class-W’ amplifier techniques -

incorporating an innovative dual-mode charge pump

architecture - to optimise efficiency and power consumption

during playback. The ground-referenced headphone and line

outputs eliminate AC coupling capacitors, and both outputs

include common mode feedback paths to reject ground

noise.

Control sequences for audio path setup can be pre-loaded

and executed by an integrated control write sequencer to

reduce software driver development and minimise pops and

clicks via Wolfson’s SilentSwitch™ technology.

The analogue input stage can be configured for single

ended or differential inputs. Up to 3 stereo microphone or

line inputs may be connected. The input impedance is

constant with PGA gain setting.

A stereo digital microphone interface is provided, with a

choice of two inputs. The analogue or digital microphone

inputs can be mixed into the headphone or line output paths.

A dynamic range controller provides compression and level

control to support a wide range of portable recording

applications in conjunction with the digital microphone

interface. Anti-clip and quick release features offer good

performance in the presence of loud impulsive noises.

ReTune

Mobile 5-band parametric equaliser with fully

programmable coefficients is integrated for optimization of

speaker characteristics. Programmable dynamic range

control is also available for maximizing loudness, protecting

speakers from clipping and preventing premature shutdown

due to battery droop.

Common audio sampling frequencies are supported from a

wide range of external clocks, either directly or generated

via the FLL.

The WM8918 can operate directly from a single 1.8V

switched supply. For optimal power consumption, the digital

core can be operated from a 1.0V supply.

WM8918

Ultra Low Power DAC for Portable Audio Applications

FEATURES



3.8mW quiescent power consumption for DAC to

headphone playback

DAC SNR 96dB typical, THD -86dB typical

2.4mW quiescent power consumption for analogue bypass

playback

Control write sequencer for pop minimised start-up and

shutdown

Single register write for default start-up sequence

Integrated FLL provides all necessary clocks



Self-clocking modes allow processor to sleep

All standard sample rates from 8kHz to 96kHz



Stereo digital microphone input

3 single ended inputs per stereo channel

1 fully differential mic / line input per stereo channel

Digital Dynamic Range Controller (compressor / limiter)

Digital sidetone mixing

Ground-referenced headphone driver

Ground-referenced line outputs

32-pin QFN package (4x4mm, 0.4mm pitch)

APPLICATIONS



Wireless headsets

Portable multimedia players

Handheld gaming

WOLFSON MICROELECTRONICS plc

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Production Data, January 2012, Rev 4.1

2012

Wolfson Microelectronics plc

Production Data

WM8918

TABLE OF CONTENTS

DESCRIPTION ....................................................................................................... 1

FEATURES ............................................................................................................ 1

APPLICATIONS..................................................................................................... 1

BLOCK DIAGRAM ................................................................................................ 2

TABLE OF CONTENTS ......................................................................................... 3

AUDIO SIGNAL PATHS DIAGRAM ...................................................................... 6

PIN CONFIGURATION .......................................................................................... 7

ORDERING INFORMATION .................................................................................. 7

PIN DESCRIPTION ................................................................................................ 8

ABSOLUTE MAXIMUM RATINGS ........................................................................ 9

RECOMMENDED OPERATING CONDITIONS ..................................................... 9

ELECTRICAL CHARACTERISTICS ................................................................... 10

TERMINOLOGY ............................................................................................................ 10

COMMON TEST CONDITIONS .................................................................................... 10

INPUT SIGNAL PATH ................................................................................................... 11

OUTPUT SIGNAL PATH ............................................................................................... 11

BYPASS PATH .............................................................................................................. 12

CHARGE PUMP ............................................................................................................ 13

FLL ................................................................................................................................ 13

OTHER PARAMETERS ................................................................................................ 13

POWER CONSUMPTION .................................................................................... 16

COMMON TEST CONDITIONS .................................................................................... 16

POWER CONSUMPTION MEASUREMENTS .............................................................. 16

SIGNAL TIMING REQUIREMENTS .................................................................... 18

COMMON TEST CONDITIONS .................................................................................... 18

MASTER CLOCK .......................................................................................................... 18

AUDIO INTERFACE TIMING ........................................................................................ 19

MASTER MODE ............................................................................................................................................................ 19

SLAVE MODE................................................................................................................................................................ 20

TDM MODE ................................................................................................................................................................... 21

CONTROL INTERFACE TIMING .................................................................................. 22

DIGITAL FILTER CHARACTERISTICS .............................................................. 23

DMIC FILTER RESPONSES ......................................................................................... 24

DMIC HIGH PASS FILTER RESPONSES .................................................................... 24

DAC FILTER RESPONSES .......................................................................................... 25

DE-EMPHASIS FILTER RESPONSES ......................................................................... 26

DEVICE DESCRIPTION ...................................................................................... 27

INTRODUCTION ........................................................................................................... 27

ANALOGUE INPUT SIGNAL PATH .............................................................................. 28

INPUT PGA ENABLE .................................................................................................................................................... 29

INPUT PGA CONFIGURATION..................................................................................................................................... 29

SINGLE-ENDED INPUT ................................................................................................................................................ 31

DIFFERENTIAL LINE INPUT ......................................................................................................................................... 31

DIFFERENTIAL MICROPHONE INPUT ........................................................................................................................ 32

INPUT PGA GAIN CONTROL ....................................................................................................................................... 32

INPUT PGA COMMON MODE AMPLIFIER .................................................................................................................. 34

ELECTRET CONDENSER MICROPHONE INTERFACE ............................................. 35

MICBIAS CONTROL ...................................................................................................................................................... 35

PD, Rev 4.1, January 2012

WM8918

Production Data

MICBIAS CURRENT DETECT ...................................................................................................................................... 36

MICBIAS CURRENT DETECT FILTERING .................................................................................................................. 37

DIGITAL MICROPHONE INTERFACE .......................................................................... 40

DIGITAL MICROPHONE VOLUME CONTROL............................................................................................................. 42

HIGH PASS FILTER ...................................................................................................................................................... 44

DYNAMIC RANGE CONTROL (DRC) ........................................................................... 45

COMPRESSION/LIMITING CAPABILITIES .................................................................................................................. 45

GAIN LIMITS .................................................................................................................................................................. 47

DYNAMIC CHARACTERISTICS ................................................................................................................................... 47

ANTI-CLIP CONTROL ................................................................................................................................................... 48

QUICK RELEASE CONTROL ....................................................................................................................................... 49

GAIN SMOOTHING ....................................................................................................................................................... 49

INITIALISATION ............................................................................................................................................................ 50

RETUNE

MOBILE PARAMETRIC EQUALIZER (EQ) ................................................ 51

DEFAULT MODE (5-BAND PARAMETRIC EQ) ........................................................................................................... 51

RETUNE MOBILE MODE........................................................................................................................................... 52

EQ FILTER CHARACTERISTICS ................................................................................................................................. 52

DIGITAL MIXING ........................................................................................................... 54

DIGITAL MIXING PATHS .............................................................................................................................................. 54

DAC INTERFACE VOLUME BOOST ............................................................................................................................ 56

DIGITAL SIDETONE ...................................................................................................................................................... 56

DIGITAL-TO-ANALOGUE CONVERTER (DAC) ........................................................... 58

DAC DIGITAL VOLUME CONTROL .............................................................................................................................. 58

DAC SOFT MUTE AND SOFT UN-MUTE ..................................................................................................................... 60

DAC MONO MIX ............................................................................................................................................................ 61

DAC DE-EMPHASIS ...................................................................................................................................................... 61

DAC SLOPING STOPBAND FILTER ............................................................................................................................ 62

DAC OVERSAMPLING RATIO (OSR) .......................................................................................................................... 62

OUTPUT SIGNAL PATH ............................................................................................... 63

OUTPUT SIGNAL PATHS ENABLE .............................................................................................................................. 64

HEADPHONE / LINE OUTPUT SIGNAL PATHS ENABLE ........................................................................................... 64

OUTPUT MUX CONTROL ............................................................................................................................................. 69

OUTPUT VOLUME CONTROL...................................................................................................................................... 69

ANALOGUE OUTPUTS ................................................................................................. 72

HEADPHONE OUTPUTS – HPOUTL AND HPOUTR ................................................................................................... 72

LINE OUTPUTS – LINEOUTL AND LINEOUTR............................................................................................................ 72

EXTERNAL COMPONENTS FOR GROUND REFERENCED OUTPUTS .................................................................... 73

REFERENCE VOLTAGES AND MASTER BIAS........................................................... 74

POP SUPPRESSION CONTROL .................................................................................. 75

DISABLED INPUT CONTROL ....................................................................................................................................... 75

CHARGE PUMP ............................................................................................................ 76

DC SERVO .................................................................................................................... 77

DC SERVO ENABLE AND START-UP ......................................................................................................................... 77

DC SERVO ACTIVE MODES ........................................................................................................................................ 80

DC SERVO READBACK ............................................................................................................................................... 82

DIGITAL AUDIO INTERFACE ....................................................................................... 82

MASTER AND SLAVE MODE OPERATION ................................................................................................................. 83

OPERATION WITH TDM ............................................................................................................................................... 83

BCLK FREQUENCY ...................................................................................................................................................... 84

AUDIO DATA FORMATS (NORMAL MODE) ................................................................................................................ 84

AUDIO DATA FORMATS (TDM MODE)........................................................................................................................ 87

DIGITAL AUDIO INTERFACE CONTROL..................................................................... 89

AUDIO INTERFACE OUTPUT TRI-STATE ................................................................................................................... 90

MICROPHONE HOOK SWITCH DETECTION .............................................................................................................. 39

PD, Rev 4.1, January 2012

Production Data

WM8918

BCLK AND LRCLK CONTROL ...................................................................................................................................... 90

COMPANDING .............................................................................................................................................................. 91

LOOPBACK ................................................................................................................................................................... 93

DIGITAL PULL-UP AND PULL-DOWN .......................................................................................................................... 93

CLOCKING AND SAMPLE RATES ............................................................................... 95

SYSCLK CONTROL ...................................................................................................................................................... 97

CONTROL INTERFACE CLOCKING ............................................................................................................................ 97

CLOCKING CONFIGURATION ..................................................................................................................................... 98

DMIC / DAC CLOCK CONTROL ................................................................................................................................... 98

OPCLK CONTROL ........................................................................................................................................................ 99

TOCLK CONTROL ........................................................................................................................................................ 99

DAC OPERATION AT 88.2K / 96K .............................................................................................................................. 100

FREQUENCY LOCKED LOOP (FLL) .......................................................................... 101

FREE-RUNNING FLL CLOCK ..................................................................................................................................... 105

GPIO OUTPUTS FROM FLL ....................................................................................................................................... 105

EXAMPLE FLL CALCULATION................................................................................................................................... 106

EXAMPLE FLL SETTINGS .......................................................................................................................................... 107

GENERAL PURPOSE INPUT/OUTPUT (GPIO) ......................................................... 108

IRQ/GPIO1 ................................................................................................................................................................... 108

BCLK/GPIO4 ................................................................................................................................................................ 109

INTERRUPTS .............................................................................................................. 110

USING IN1L AND IN1R AS INTERRUPT INPUTS ...................................................................................................... 114

CONTROL INTERFACE .............................................................................................. 115

CONTROL WRITE SEQUENCER ............................................................................... 117

INITIATING A SEQUENCE .......................................................................................................................................... 117

PROGRAMMING A SEQUENCE ................................................................................................................................ 118

DEFAULT SEQUENCES ............................................................................................................................................. 121

START-UP SEQUENCE .............................................................................................................................................. 121

SHUTDOWN SEQUENCE ........................................................................................................................................... 123

POWER-ON RESET .................................................................................................... 125

QUICK START-UP AND SHUTDOWN ........................................................................ 127

QUICK START-UP (DEFAULT SEQUENCE) .............................................................................................................. 127

FAST START-UP FROM STANDBY ........................................................................................................................... 127

QUICK SHUTDOWN (DEFAULT SEQUENCE)........................................................................................................... 128

SOFTWARE RESET AND CHIP ID ............................................................................. 129

APPLICATIONS INFORMATION ...................................................................... 173

RECOMMENDED EXTERNAL COMPONENTS ......................................................... 173

MIC DETECTION SEQUENCE USING MICBIAS CURRENT ..................................... 175

PACKAGE DIMENSIONS .................................................................................. 177

IMPORTANT NOTICE ....................................................................................... 178

ADDRESS .......................................................................................................... 178

PD, Rev 4.1, January 2012

WM8918CGEFL/RV Related Products

	WM8918CGEFL/RV	WM8918CGEFL/V
Description	Consumer Circuit, CMOS, PQCC32, 4 X 4 MM, 0.75 MM HEIGHT, 0.40 MM PITCH, LEAD FREE, PLASTIC, QFN-32	Consumer Circuit, CMOS, PQCC32, 4 X 4 MM, 0.75 MM HEIGHT, 0.40 MM PITCH, LEAD FREE, PLASTIC, QFN-32
Is it Rohs certified?	conform to	conform to
Objectid	8077929122	8077929123
package instruction	HVQCCN,	HVQCCN,
Reach Compliance Code	compliant	compliant
Other features	IT ALSO REQUIRES ANALOG SUPPLY RANGE 1.71 TO 2 VOLT	IT ALSO REQUIRES ANALOG SUPPLY RANGE 1.71 TO 2 VOLT
Commercial integrated circuit types	CONSUMER CIRCUIT	CONSUMER CIRCUIT
JESD-30 code	S-PQCC-N32	S-PQCC-N32
length	4 mm	4 mm
Number of functions	1	1
Number of terminals	32	32
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	HVQCCN	HVQCCN
Package shape	SQUARE	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Maximum seat height	0.8 mm	0.8 mm
Maximum supply voltage (Vsup)	1.98 V	1.98 V
Minimum supply voltage (Vsup)	0.95 V	0.95 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal form	NO LEAD	NO LEAD
Terminal pitch	0.4 mm	0.4 mm
Terminal location	QUAD	QUAD
width	4 mm	4 mm

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