A54SX32A-TQ144M datasheet, PDF

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A54SX32A-TQ144M: DescriptionFPGA - Field Programmable Gate Array SXA; Categorysemiconductor Programmable logic devices; File Size407KB，51 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com

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A54SX32A-TQ144M Overview

FPGA - Field Programmable Gate Array SXA

A54SX32A-TQ144M Parametric

Parameter Name	Attribute value
Product Attribute	Attribute Value
Manufacturer	Microsemi
Product Category	FPGA - Field Programmable Gate Array
Shipping Restrictions	This product may require additional documentation to export from the United States.
RoHS	N
Number of I/Os	113 I/O
Operating Supply Voltage	2.5 V
Minimum Operating Temperature	- 55 C
Maximum Operating Temperature	+ 125 C
Mounting Style	SMD/SMT
Package / Case	TQFP-144
Height	1.4 mm
Length	20 mm
Width	20 mm
Number of Gates	48000
Maximum Operating Frequency	238 MHz
Moisture Sensitive	Yes
Factory Pack Quantity	60
Supply Voltage - Max	2.75 V
Supply Voltage - Min	2.25 V
Unit Weight	0.046530 oz

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v2.0

HiRel SX-A Family FPGAs

Features and Benefits

Leading Edge Performance

•

215 MHz System Performance (Military Temperature)

5.3 ns Clock-to-Out (Pin-to-Pin) (Military Temperature)

240 MHz Internal Performance (Military Temperature)

•

Actel Secure Programming Technology with

FuseLock™ Prevents Reverse Engineering and Design

Theft

Cold-Sparing Capability

Individual Output Slew Rate Control

QML Certified Devices

100% Military Temperature Tested (–55°C to +125°C)

33 MHz PCI Compliant

CPLD and FPGA Integration

Single-Chip Solution

Configurable I/O Support for 3.3 V/5 V PCI, LVTTL,

and TTL

Configurable Weak Resistor Pull-Up or Pull-Down for

Tristated Outputs during Power-Up

Up to 100% Resource Utilization and 100% Pin

Locking

2.5 V, 3.3 V, and 5 V Mixed Voltage Operation with

5 V Input Tolerance and 5 V Drive Strength

Very Low Power Consumption

Deterministic, User-Controllable Timing

Unique In-System Diagnostic and Verification

Capability with Silicon Explorer II

Boundary-Scan Testing in Compliance with IEEE

1149.1 (JTAG)

A54SX32A

32,000

48,000

2,880

1,800

1,080

1,980

228

Yes

5.3 ns

0 ns

Std, –1

84, 208, 256

A54SX72A

72,000

108,000

6,036

4,024

2,012

4,024

213

Yes

6.7 ns

0 ns

Std, –1

208, 256

Specifications

•

48,000 to 108,000 Available System Gates

Up to 228 User-Programmable I/O Pins

Up to 2,012 Dedicated Flip-Flops

0.25/0.22 µ CMOS Process Technology

Features

•

Hot-Swap Compliant I/Os

Power-Up/Down Friendly (no sequencing required

for supply voltages)

Class B Level Devices

Three Standard Hermetic Package Options

•

Product Profile

Device

Capacity

Typical Gates

System Gates

Logic Modules

Combinatorial Cells

Dedicated Flip-Flops

Maximum Flip-Flops

Maximum User I/Os

Global Clocks

Quadrant Clocks

Boundary-Scan Testing

3.3 V / 5 V PCI

Clock-to-Out

Input Set-Up (External)

Speed Grades

Package (by Pin Count)

CQFP

N o ve m b e r 2 0 0 6

See the Actel website for the latest version of the datasheet.

HiRel SX-A Family FPGAs

Table of Contents

General Description

QML Certification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

HiRel SX-A Family Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9

Detailed Specifications

2.5 V/3.3 V/5 V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10

5 V PCI Compliance for the HiRel SX-A Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12

3.3 V PCI Compliance for the HiRel SX-A Family . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14

Junction Temperature (T

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16

Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16

HiRel SX-A Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17

Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31

Package Pin Assignments

84-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

208-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

256-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

Datasheet Information

List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

International Traffic in Arms Regulations (ITAR) and Export Administration

Regulations (EAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

v 2 .0

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