Philips Semiconductors
Product data sheet
8-channel I
2
C switch with reset
PCA9548
DESCRIPTION
The PCA9548 is a octal bi-directional translating switch controlled
by the I
2
C-bus. The SCL/SDA upstream pair fans out to eight
downstream pairs, or channels. Any individual SCx/SDx channel or
combination of channels can be selected, determined by the
contents of the programmable Control Register.
An active-LOW reset input allows the PCA9548 to recover from a
situation where one of the downstream I
2
C-buses is stuck in a LOW
state. Pulling the RESET pin LOW resets the I2C state machine and
causes all the channels to be deselected as does the internal power
on reset function.
The pass gates of the switches are constructed such that the V
DD
pin can be used to limit the maximum high voltage which will be
passed by the PCA9548. This allows the use of different bus
voltages on each pair, so that 1.8 V, 2.5 V, or 3.3 V parts can
communicate with 5 V parts without any additional protection.
External pull-up resistors pull the bus up to the desired voltage level
for each channel. All I/O pins are 5 V tolerant.
FEATURES
•
1-of-8 bi-directional translating switches
•
I
2
C interface logic; compatible with SMBus standards
•
Active LOW Reset Input
•
3 address pins allowing up to 8 devices on the I
2
C-bus
•
Channel selection via I
2
C-bus, in any combination
•
Power-up with all switch channels deselected
•
Low Rds
ON
switches
•
Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and
•
No glitch on power-up
•
Supports hot insertion
•
Low stand-by current
•
Operating power supply voltage range of 2.3 V to 5.5 V
•
5 V tolerant Inputs
•
0 kHz to 400 kHz clock frequency
•
ESD protection exceeds 2000 V HBM per JESD22-A114,
•
Latchup testing is done to JESDEC Standard JESD78 which
•
Packages offered: SO24, TSSOP24
ORDERING INFORMATION
PACKAGES
24-Pin Plastic SO
TEMPERATURE RANGE
–40
°C
to +85
°C
exceeds 100 mA
150 V MM per JESD22-A115 and 1000 V per JESD22-C101
5 V buses
ORDER CODE
PCA9548D
DRAWING NUMBER
SOT137-1
SOT355-1
24-Pin Plastic TSSOP
–40
°C
to +85
°C
PCA9548PW
Standard packing quantities and other packaging data are available at www.standardproducts.philips.com/packaging.
2004 Sep 30
2
Philips Semiconductors
Product data sheet
8-channel I
2
C switch with reset
PCA9548
DEVICE ADDRESSING
Following a START condition the bus master must output the
address of the slave it is accessing. The address of the PCA9548 is
shown in Figure 3. To conserve power, no internal pullup resistors
are incorporated on the hardware selectable address pins and they
must be pulled HIGH or LOW.
Table 1. Control Register; Write — Channel Selection/
Read — Channel Status
B7
B6
B5
B4
B3
B2
B1
B0
0
X
X
X
X
X
X
X
1
COMMAND
Channel 0
disabled
Channel 0
enabled
Channel 1
disabled
Channel 1
enabled
Channel 2
disabled
Channel 2
enabled
Channel 3
disabled
Channel 3
enabled
Channel 4
disabled
Channel 4
enabled
Channel 5
disabled
Channel 5
enabled
Channel 6
disabled
Channel 6
enabled
Channel 7
disabled
Channel 7
enabled
1
1
1
0
A2
A1 A0 R/W
0
X
X
X
X
X
X
1
SW00915
X
FIXED
HARDWARE SELECTABLE
Figure 3. Slave address
The last bit of the slave address defines the operation to be
performed. When set to logic 1, a read is selected while a logic 0
selects a write operation.
X
X
X
X
X
0
X
1
0
X
X
X
X
1
0
X
X
X
1
0
X
X
1
0
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 5
CHANNEL 6
CHANNEL 7
X
X
X
X
CONTROL REGISTER
Following the successful acknowledgement of the slave address,
the bus master will send a byte to the PCA9548, which will be stored
in the control register. If multiple bytes are received by the
PCA9548, it will save the last byte received. This register can be
written and read via the I
2
C-bus.
CHANNEL SELECTION BITS
(READ/WRITE)
7
B7
6
B6
5
B5
4
B4
3
B3
2
B2
1
B1
0
B0
X
X
X
X
X
X
X
X
X
X
1
0
X
1
X
X
X
X
X
X
X
X
X
X
X
X
SW00932
0
0
0
0
0
0
0
0
Figure 4. Control register
No channel
selected;
power-up/reset
default state
CONTROL REGISTER DEFINITION
One or several SCx/SDx downstream pair, or channel, is selected
by the contents of the control register. This register is written after
the PCA9548 has been addressed. The 2 LSBs of the control byte
are used to determine which channel is to be selected. When a
channel is selected, the channel will become active after a stop
condition has been placed on the I
2
C-bus. This ensures that all
SCx/SDx lines will be in a HIGH state when the channel is made
active, so that no false conditions are generated at the time of
connection.
NOTE:
Several channels can be enabled at the same time.
Ex: B7 = 0, B6 = 1, B5 = 0, B4 = 0, B3 = 1, B2 = 1, B1 = 0, B0 = 0,
means that channels 7, 5, 4, 1, and 0 are disabled and channels 6,
3, and 2 are enabled.
Care should be taken not to exceed the maximum bus capacitance.
RESET INPUT
The RESET input is an active-LOW signal which may be used to
recover from a bus fault condition. By asserting this signal LOW for
a minimum of t
WL
, the PCA9548 will reset its registers and I
2
C state
machine and will deselect all channels. The RESET input must be
connected to V
DD
through a pull-up resistor.
POWER-ON RESET
When power is applied to V
DD
, an internal Power On Reset holds
the PCA9548 in a reset state until V
DD
has reached V
POR
. At this
point, the reset condition is released and the PCA9548 registers and
I
2
C state machine are initialized to their default states, all zeroes
causing all the channels to be deselected.
2004 Sep 30
5
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