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71V3556SA133BQ

Description
SRAM 4M X36 3.3V I/O SLOW ZBT
Categorystorage    storage   
File Size502KB,25 Pages
ManufacturerIDT (Integrated Device Technology)
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71V3556SA133BQ Overview

SRAM 4M X36 3.3V I/O SLOW ZBT

71V3556SA133BQ Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codeCABGA
package instructionTBGA, BGA165,11X15,40
Contacts165
Manufacturer packaging codeBQ165
Reach Compliance Codenot_compliant
ECCN code3A991.B.2.A
Samacsys DescriptionCHIP ARRAY BGA 13.0 X 15.0 MM X 1.0 MM P
Maximum access time4.2 ns
Maximum clock frequency (fCLK)133 MHz
I/O typeCOMMON
JESD-30 codeR-PBGA-B165
JESD-609 codee0
length15 mm
memory density4718592 bit
Memory IC TypeZBT SRAM
memory width36
Humidity sensitivity level3
Number of functions1
Number of terminals165
word count131072 words
character code128000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize128KX36
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTBGA
Encapsulate equivalent codeBGA165,11X15,40
Package shapeRECTANGULAR
Package formGRID ARRAY, THIN PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)225
power supply3.3 V
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum standby current0.04 A
Minimum standby current3.14 V
Maximum slew rate0.3 mA
Maximum supply voltage (Vsup)3.465 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn63Pb37)
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperature20
width13 mm
IDT71V3556S/XS
128K x 36, 256K x 18
3.3V Synchronous ZBT SRAMs
IDT71V3558S/XS
3.3V I/O, Burst Counter
IDT71V3556SA/XSA
Pipelined Outputs
IDT71V3558SA/XSA
Features
128K x 36, 256K x 18 memory configurations
Supports high performance system speed - 200 MHz (x18)
(3.2 ns Clock-to-Data Access)
Supports high performance system speed - 166 MHz (x36)
(3.5 ns Clock-to-Data Access)
ZBT
TM
Feature - No dead cycles between write and read
cycles
Internally synchronized output buffer enable eliminates the
need to control
OE
Single R/W (READ/WRITE) control pin
Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
4-word burst capability (interleaved or linear)
Individual byte write (BW
1
-
BW
4
) control (May tie active)
Three chip enables for simple depth expansion
3.3V power supply (±5%), 3.3V I/O Supply (V
DDQ)
Optional- Boundary Scan JTAG Interface (IEEE 1149.1
compliant)
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array (fBGA)
Description
The IDT71V3556/58 are 3.3V high-speed 4,718,592-bit (4.5 Mega-
bit) synchronous SRAMS. They are designed to eliminate dead bus
cycles when turning the bus around between reads and writes, or
writes and reads. Thus, they have been given the name ZBT
TM
, or
Zero Bus Turnaround.
Address and control signals are applied to the SRAM during one
clock cycle, and two cycles later the associated data cycle occurs, be
it read or write.
The IDT71V3556/58 contain data I/O, address and control signal
registers. Output enable is the only asynchronous signal and can be
used to disable the outputs at any given time.
A Clock Enable (CEN) pin allows operation of the IDT71V3556/58
to be suspended as long as necessary. All synchronous inputs are
ignored when (CEN) is high and the internal device registers will hold
their previous values.
There are three chip enable pins (CE
1
, CE
2
,
CE
2
) that allow the
user to deselect the device when desired. If any one of these three are
not asserted when ADV/LD is low, no new memory operation can be
initiated. However, any pending data transfers (reads or writes) will be
completed. The data bus will tri-state two cycles after chip is deselected
or a write is initiated.
Pin Description Summary
A
0
-A
17
CE
1
, CE
2
,
CE
2
OE
R/W
CEN
BW
1
,
BW
2
,
BW
3
,
BW
4
CLK
ADV/LD
LBO
TMS
TDI
TCK
TDO
TRST
ZZ
I/O
0
-I/O
31
, I/O
P1
-I/O
P4
V
DD
, V
DDQ
V
SS
Address Inputs
Chip Enables
Output Enable
Read/Write Signal
Clock Enable
Individual Byte Write Selects
Clock
Advance burst address / Load new address
Linear / Interleaved Burst Order
Test Mode Select
Test Data Input
Test Clock
Test Data Output
JTAG Reset (Optional)
Sleep Mode
Data Input / Output
Core Power, I/O Power
Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
I/O
Supply
Supply
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Static
Synchronous
Synchronous
N/A
Synchronous
Asynchronous
Synchronous
Synchronous
Static
Static
5281 tbl 01
JANUARY 2015
1
©
2015 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-5281/12
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