Intel® Atom™ Processor D2000 and
N2000 Series
Datasheet - Volume 1 of 2
Refer to Doc ID 326137-003 for Volume 2 of 2
July 2012
Revision 003
Document Number: 326136-003
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2
Datasheet - Volume 1 of 2
Contents
1
Introduction
............................................................................................................. 9
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2
Intel® Atom™ Processor D2000 Series and N2000 Series Features ............................ 9
System Memory Features ................................................................................... 10
Direct Media Interface Features........................................................................... 11
Graphics Processing Unit Features ....................................................................... 11
Video............................................................................................................... 12
Clocking........................................................................................................... 13
Power Management ........................................................................................... 13
1.7.1 Terminology .......................................................................................... 14
References ....................................................................................................... 15
System Block Diagram ....................................................................................... 16
1.9.1 PHOLD limitation on Legacy Feature.......................................................... 16
CPU Legacy Signal............................................................................................. 18
System Memory Interface .................................................................................. 20
DMI - Direct Media Interface ............................................................................... 22
PLL Signals....................................................................................................... 23
Analog Display Signals ....................................................................................... 23
LVDS Signals .................................................................................................... 24
DDI Audio Interface........................................................................................... 25
DDI Port 0........................................................................................................ 27
DDI Port1......................................................................................................... 28
JTAG/ITP Signals............................................................................................... 28
Error and Thermal Protection .............................................................................. 29
Processor Core Power Signals ............................................................................. 29
Graphics, DMI and Memory Core Power Signals ..................................................... 30
Ground ............................................................................................................ 31
System Memory Controller ................................................................................. 32
3.1.1 System Memory Organization Modes......................................................... 32
3.1.2 System Memory Technology Supported ..................................................... 32
3.1.3 Rules for populating DIMM Slots ............................................................... 34
Graphics Processing Unit .................................................................................... 34
3.2.1 3-D Core Key Features ............................................................................ 34
3.2.2 2D Engine ............................................................................................. 38
3.2.3 Analog Display Port Characteristics ........................................................... 39
3.2.4 Digital Display Interfaces......................................................................... 40
3.2.5 Multiple Display Configurations................................................................. 46
Thermal Sensor................................................................................................. 46
3.3.1 PCI Device 0, Function 0 ......................................................................... 46
Power Management ........................................................................................... 47
3.4.1 Interface Power States Supported ............................................................ 47
3.4.2 Intel® Hyper-Threading Technology ......................................................... 47
Power and Ground Balls ..................................................................................... 48
Decoupling Guidelines ........................................................................................ 48
4.2.1 Voltage Rail Decoupling........................................................................... 48
Signal Description
................................................................................................... 17
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
3
Functional Description
............................................................................................. 32
3.1
3.2
3.3
3.4
4
Electrical Specifications
........................................................................................... 48
4.1
4.2
Datasheet - Volume 1 of 2
3
4.3
4.4
4.5
4.6
4.7
4.8
4.9
Processor Clocking .............................................................................................49
4.3.1 PLL Power Supply ...................................................................................49
Voltage Identification (VID).................................................................................50
Catastrophic Thermal Protection ..........................................................................56
Reserved or Unused Signals ................................................................................56
Signal Groups ...................................................................................................57
Test Access Port (TAP) Connection .......................................................................57
DC Specifications ...............................................................................................57
4.9.1 Flexible Motherboard Guidelines (FMB) ......................................................57
4.9.2 Voltage and Current Specifications ............................................................58
4.9.3 DC Specifications ....................................................................................64
Mechanical Specifications ...................................................................................74
5.1.1
Mechanical Drawings ..............................................................................74
5.1.2
Loading Specifications ............................................................................75
Processor Ballout Assignment ..............................................................................75
Signal
6.1.1
6.1.2
6.1.3
Quality Specifications and Measurement Guidelines.......................................94
Overshoot/Undershoot Guidelines .............................................................94
Overshoot/Undershoot Magnitude .............................................................95
Overshoot/Undershoot Pulse Duration .......................................................95
5
Mechanical Specifications and Ball Information
.......................................................74
5.1
5.2
6
Signal Quality Specifications
....................................................................................94
6.1
7
Power Management
.................................................................................................97
7.1
ACPI state Supported .........................................................................................97
7.1.1 System States........................................................................................97
7.1.2 Processor Idle States...............................................................................97
7.1.3 Integrated Graphics Display States ...........................................................98
7.1.4 Integrated Memory Controller States .........................................................98
7.1.5 DMI States ............................................................................................98
7.1.6 Interface State Combinations ...................................................................99
Processor Core Power Management ......................................................................99
7.2.1 Enhanced Intel SpeedStep® Technology .................................................. 100
7.2.2 Dynamic Cache Sizing ........................................................................... 100
7.2.3 Low-Power Idle States........................................................................... 101
7.2.4 Graphics Power Management.................................................................. 103
7.2.5 Thread C-state Description..................................................................... 105
7.2.6 Processor Core/ C-states Description ....................................................... 106
7.2.7 Package C-States ................................................................................. 107
IMC Power Management ................................................................................... 110
7.3.1 Disabling Unused System Memory Outputs............................................... 110
7.3.2 DRAM Power Management and Initialization ............................................. 111
DMI Power Management ................................................................................... 112
7.4.1 Stop-Grant State .................................................................................. 112
7.4.2 Stop-Grant Snoop State ........................................................................ 113
7.4.3 Deep Sleep State.................................................................................. 113
7.4.4 Deeper Sleep State ............................................................................... 113
7.4.5 Extended Low-Power States ................................................................... 113
Thermal Specifications...................................................................................... 115
8.1.1 Intel® Thermal Monitor ......................................................................... 116
8.1.2 Digital Thermal Sensor .......................................................................... 118
8.1.3 Out of Specification Detection................................................................. 119
7.2
7.3
7.4
8
Thermal Specifications and Design Considerations.................................................
115
8.1
4
Datasheet - Volume 1 of 2
8.1.4
9
9.1
9.2
10
PROCHOT# Signal Pin ........................................................................... 119
Testability
............................................................................................................ 120
JTAG Boundary Scan........................................................................................ 120
TAP Instructions and Opcodes ........................................................................... 121
Debug Tool Specifications......................................................................................
122
Figures
1-1 Intel® Atom™ D2000 series/N2000 series System Block Diagram .................................. 16
3-2 LVDS Signals and Swing Voltage ................................................................................ 40
3-3 LVDS Clock and Data Relationship .............................................................................. 41
3-4 Panel Power Sequencing ........................................................................................... 42
3-5 HDMI Overview........................................................................................................ 43
3-6 DP Overview ........................................................................................................... 44
4-7 Vcc and Icc Processor Loadline................................................................................... 59
4-8 Vcc AC Vs. DC Loadline ............................................................................................. 60
4-9 Definition of Differential Voltage and Differential Voltage Peak-to-Peak............................ 72
4-10Definition of Pre-emphasis ........................................................................................ 72
5-11 Mechanical Drawings ............................................................................................... 74
5-12 Pinmap (Top View, Upper-Left Quadrant) ................................................................... 75
5-13 Pinmap (Top View, Upper-Right Quadrant) ................................................................. 76
5-14 Pinmap (Top View, Lower-Left Quadrant) ................................................................... 77
5-15Pinmap (Top View, Lower-Right Quadrant) .................................................................. 78
6-16Overshoot, Undershoot, and Ringback Illustration ........................................................ 96
7-17Idle Power Management Breakdown of the Processor Cores ......................................... 102
7-18Thread and Core C-state Entry and Exit .................................................................... 102
7-19Processor Core Low-Power States............................................................................. 103
7-20Package C-state Entry and Exit ................................................................................ 108
9-21JTAG Boundary Scan Test Mode Initialization Cycles ................................................... 120
Tables
1-1 Summary of the Resolution of Graphic interface ........................................................... 12
1-2 The Display core clock Frequency by Skus ................................................................... 13
1-3 27 MHz Requirement Range ...................................................................................... 13
2-4 Signal Type ............................................................................................................. 17
2-5 Signal Description Buffer Types.................................................................................. 17
2-6 CPU Legacy Signal ................................................................................................... 18
2-7 Memory Channel A ................................................................................................... 20
2-8 Memory Reference and Compensation......................................................................... 21
2-9 Reset and Miscellaneous Signal .................................................................................. 21
2-10DMI - Processor to Intel NM10 Express Chipset Serial Interface ...................................... 22
2-11PLL Signals ............................................................................................................. 23
2-12Analog Display Signals.............................................................................................. 23
2-13LVDS Signals........................................................................................................... 24
2-14DDI Audio Signals .................................................................................................... 25
2-15DDI Port 0 .............................................................................................................. 27
2-16DDI Port 1 .............................................................................................................. 28
2-17JTAG/ITP Signals ..................................................................................................... 28
2-18Error and Thermal Protection ..................................................................................... 29
2-19Processor Core Power Signals .................................................................................... 29
2-20Power Signals.......................................................................................................... 30
2-21Ground ................................................................................................................... 31
Datasheet - Volume 1 of 2
5
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