Datasheet
BD555BKFV AC/DC Controller IC
for mains dimmable LED lighting
BD555BKFV
●General
Description
The BD555BKFV controller AC/DC controller IC can be
used in a wide range of dimmable LED lighting driver
applications. The main target application is dimmable
retro-fit LED lighting, replacing existing incandescent
light bulbs, halogen spot lights, CFL tubes etc.
●Features
Fixed frequency DC/DC controller (selectable)
Peak current or average current control (PCC/ACC)
Dynamic Load Current Controller (DLCC)
Logarithmic compensation of detected dimming level
Dimmer detector function
Anti-flash function when dimmer is OFF
PWM and analog dimming control supported
Over Current Protection (OCP)
Thermal Shutdown protection (TSD)
Under Voltage Lock Out (UVLO)
●Applications
Retro-fit dimmable LED lighting (E27, E14, GU10, T8
etc.). Wide range of TRIAC and transistor dimmers
supported by DLCC function.
Custom LED lighting with PWM or voltage controlled
dimming.
●Key
Specifications
Input voltage range........................................16~39V
Regulated supply voltage.................................11.5V
Fixed DC/DC operating frequency.........40~400kHz
Detectable phase-cut range........................45°~135°
Typical current consumption.............................1mA
Under Voltage Lock Out detection.....................9.0V
Operating temperature range.................-40~+110°C
●Package
SSOP-B14
W(Typ.) x D(Typ.) x H(Max.)
5.00mm x 6.40mm x 1.15mm
●Typical
Application Circuits
Figure 1.
Typical application circuit for non-isolated dimmable buck topology
○Product
structure：Silicon monolithic integrated circuit
.
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○This
product is not designed protection against radioactive rays
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BD555BKFV
●Pin
Configuration
Datasheet
Figure 2. Pin configuration
Figure 3. Equivalent circuit
●Pin
Description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
*1
*2
*3
*4
Pin name
BLDR
WBLD
ISYS
*1
GND
DIM
DET
REF
*2
OSC
*2
FB
*3
ISNS
PGND
*4
SW
VDDH
SUP
I/O
Out
In
In/Out
-
In/Out
In
Out
Out
In
In
-
Out
In/Out
In
Function
Driver for dynamic load current controller (DLCC) transistor
Internal strong load current input (connected to internal ‘open drain’ NMOS)
Sense voltage input for DLCC ON/OFF function
Ground terminal
Detected dimming level reference voltage
Input for detecting phase-cut angle
Pin for external resistor to set LED current (average current control mode)
Pin for external resistor to set DC/DC operating frequency
Average current feedback input or PCC mode selection (V
FB
<1.5V)
Sense voltage for peak current regulation & over current protection (OCP)
Ground terminal for internal BLDR and SW driver stages
Driver output for gate of external DC/DC switching MOSFET
Regulated supply voltage
Input supply voltage
Between ISYS and GND are internal anti-parallel surge diodes
Connect only resistive load according to application instructions
FB terminal is ‘pre-charged’ to 4V during start-up in order to have smooth start of the LED current regulation. Never connect this pin directly to GND.
Between GND and PGND are internal anti-parallel diodes
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BD555BKFV
●Block
Diagram
Datasheet
Figure 4.
Block diagram
●Description
of Blocks
Startup sequence:
When an AC input voltage is applied, the rectified mains voltage (VHV) is buffered by capacitor C2 and
starts supplying the BD555BKFV via start-up resistor R6. The VDDH capacitor C5 will be charged by the internal regulator until
the system UVLO condition is released, after which a PWM signal from terminal SW can start driving the external NMOS when
the anti-flash detector is released.
Anti-flash detector:
Some dimmers require a small leakage current to power an internal electronic control circuit or an indicator
LED. In order to prevent a ‘false start’ when the VHV buffer cap was accidentally charged by this leakage current, the detection
level voltage on the DIM terminal needs to rise above 400mV, before the SW terminal starts switching, lighting up the LEDs.
DC/DC buck converter:
When the SW signal is high, it turns ON the MN2 MOSFET, building up a current in coil L1 via the LED
string. During the OFF period of MN2, the current flows via fly-back diode D4. Capacitor C4 stabilizes the LED voltage to reduce
the LED current ripple. The LED current is regulated by controlling the LED forward voltage.
Auxiliary supply voltage:
The alternating current in the primary side of inductor L1 is coupled n
p
:n
s
to the secondary side,
creating a voltage alternating between V
VHV
(MN2=ON) and (V
LED
+ V
th,D4
)* n
s
/n
p
(MN2=OFF). This last voltage is passed on to
capacitor C3 via diode D5. This creates an auxiliary supply which improves efficiency by reducing the resistive power loss in the
start-up resistor R6.
LED average current control (ACC) mode:
The BD555BKFV features two feedback mechanisms by average current control
(ACC) or peak current control (PCC). In ACC mode, the high-side sensing resistor R7 is used in the LED current mirror (typically
1:500), creating an LED feedback current in transistor Q1. This current flows to the FB terminal and creating a reference voltage
(for LED current regulation) across resistor R12 at the REF terminal.
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BD555BKFV
Datasheet
LED peak current control (PCC) mode:
Alternatively, in PCC mode (V
FB
<1.5V), the duty-cycle of the SW signal is determined
by the ‘peak current’ through resistor R10. The ISNS terminal senses the voltage across resistor R10. When this voltage
reaches the reference voltage, the SW signal will be pulled low. During startup and in ACC mode, this function is used as ‘Over
Current Protection’ to limit the current through inductor L1. In both ACC and PCC mode, the REF voltage will be adjusted to the
detected phase-cut in case a dimmer is connected.
Phase-cut detection:
via resistive divider R4/R5 at the DET terminal, the rising and falling edge of the phase-cut are detected,
generating an internal PWM signal. Via an internal resistor and external capacitor C1, this PWM signal is averaged into a
dimming reference voltage at the DIM terminal. An internal conversion function creates a logarithmically corrected voltage at the
REF terminal. This allows achieving a ‘natural’ LED light intensity curve as perceived by the human eye, when turning the
dimmer knob.
Dimmer stability:
based on the phase-cut detection at the DET terminal, the DLCC dynamically adjusts the total load current
for stable operation of ‘leading edge’ TRIAC dimmers. For ‘trailing edge’ dimmers, the DLCC load current pulls down the dimmer
output voltage, in order to detect the falling edge. In case the VHV current exceeds the minimum load current requirement, the
DLCC load current can disabled completely. This allows to achieve high efficiency without dimmers.
Dimmer detector:
when a dimmer is not present, the DLCC will be switched OFF.
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BD555BKFV
●Absolute
Maximum Ratings
Parameter
Supply voltage (SUP terminal)
Internal supply regulator voltage (VDDH terminal)
SW output current
BLDR output current
WLBD, ISNS terminal voltage
WBLD input current (strong load current)
DIM, DET, OSC, REF, FB terminal voltage
FB input current (V
FB
=4.5V)
ISYS, PGND terminal voltage
Operating frequency
Maximum power dissipation
Operating ambient temperature range
Storage temperature range
Maximum junction temperature
Symbol
V
SUP
V
VDDH
I
SW
I
BLDR
V
WBLD
, V
ISNS
I
SBLD
V
DIM
, V
DET
, V
OSC
, V
REF
, V
FB
I
FB
V
ISYS
, V
PGND
f
operating
P
d
T
a
T
storage
T
junction,max
Maximum rating
40
15.5
600
*1
60
*1
15.5
300
*2
4.5
4.0
+/- 0.5
400
0.87
*4
-40
½
+110
-55
½
+150
+150
Datasheet
Unit
V
V
mA
mA
V
mA
V
mA
V
kHz
W
°C
°C
°C
*1 I
SW
pulse current duration <100ns@f
operating
*2 I
BLDR
pulse current duration <1us@f
mains
never exceed 0.8*Pd
*3 I
WBLD
pulse current duration <300us@f
mains
*4 SSOP-B14 package thermal resistance R
θJA
=143°C/W, mounted on a two-layer PCB of 70x70x1.6mm
3
Notice1: Due to in case of the applied voltage or operating ambient temperature range or etc. exceed the absolute maximum ratings, a damage maybe
occurs, and the damage mode (short or open or etc.) can not be supposed, please take a physical safety measure (such as add a fuse) while some special
modes in which the absolute maximum ratings may be exceeded are considered.
Notice2: The power dissipation in BD555BKFV is mainly decided by the switching frequency of the DCDC converter and the current which is applied to the
BLDR pin. Please make the power dissipation caused by those less than 80% of the maximum power dissipation of the package.
●Recommended
Operating Range (Ta= -40 ~ +110°C)
Parameter
Supply voltage
Symbol
VSUP
Range
16
~
39
Unit
V
●Electrical
Characteristics
Parameter
Internal Supply Regulator*
1
Startup current
Supply current ON
Supply current ON 1
Supply current ON 2
VDDH internal regulator voltage
UVLO release voltage
UVLO trigger voltage
UVLO hysteresis
Switching regulator
Minimum frequency
Maximum frequency
SW maximum duty cycle
f
SW_min
f
SW_max
δ
max
32
320
70
40
400
75
48
480
80
kHz
kHz
%
6
±20%
,
f
SW
= 9.0×10 /R11 (kHz)
for frequency range 40KHz to 400KHz.
Symbol
Limits
Min.
Typ.
Max.
Unit
Comments
I
SUP,start
I
SUP,NS
I
SUP,ON1
I
SUP,ON2
V
VDDH
V
UVLO,rl
V
UVLO,tr
V
UVLO,hys
-
-
-
-
10.0
9.20
0.4
0.8
1.0
2
11.5
10.0
0.8
1.0
1.3
2.4
15.0
10.8
mA
mA
mA
mA
V
V
V
V
In UVLO condition
No switching.
No load on SW/BLDR,
f
SW
=40kHz.
No load on SW/BLDR,
f
SW
=400kHz.
VDDH load current I
VDDH
< 10mA
VDDH rising
VDDH falling
V
UVLO,tr
- V
UVLO,hys
0.75
1.00
1.25
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