DS21Q50
Quad E1 Transceiver
www.maxim-ic.com
GENERAL DESCRIPTION
The DS21Q50 E1 quad transceiver contains all the
necessary functions for connecting to four E1 lines.
The on-board clock/data recovery circuitry coverts
the AMI/HDB3 E1 waveforms to an NRZ serial
stream. The DS21Q50 automatically adjusts to E1
22AWG (0.6mm) twisted-pair cables from 0km to
over 2km in length. The device can generate the
necessary G.703 waveshapes for both 75W coax and
120W twisted-pair cables. The on-board jitter
attenuators (selectable to either 32 bits or 128 bits)
can be placed in either the transmit or receive data
paths. The framers locate the frame and multiframe
boundaries and monitor the data streams for alarms.
The device contains a set of internal registers, from
which the user can access and control the operation
of the unit by the parallel control port or serial port.
The device fully meets all the latest E1 specifications
including ITU-T G.703, G.704, G.706, G.823, G.732,
and I.431 ETS 300 011, ETS 300 233, and ETS 300
166 as well as CTR12 and CTR4.
FEATURES
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Four Complete E1 (CEPT) PCM-30/ISDN-PRI
Transceivers
Long-Haul and Short-Haul Line Interfaces
32-Bit or 128-Bit Crystal-Less Jitter Attenuator
Frames to FAS, CAS, CCS, and CRC4 Formats
4MHz/8MHz/16MHz Clock Synthesizer
Flexible System Clock with Automatic Source
Switching on Loss-of-Clock Source
Two-Frame Elastic-Store Slip Buffer on the
Receive Side
Interleaving PCM Bus Operation Up to
16.384MHz
Configurable Parallel and Serial Port Operation
Detects and Generates Remote and AIS Alarms
Fully Independent Transmit and Receive
Functionality
Four Separate Loopback Functions
PRBS Generation/Detection/Error Counting
3.3V Low-Power CMOS
Large Counters for Bipolar and Code Violations,
CRC4 Codeword Errors, FAS Word Errors, and
E Bits
Eight Additional User-Configurable Output Pins
100-Pin, 14mm x 14mmLQFP Package
APPLICATIONS
DSLAMs
Routers
IMA and WAN Equipment
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PIN CONFIGURATION
TOP VIEW
ORDERING INFORMATION
PART
DS21Q50L
DS21Q50LN
TEMP RANGE
0°C to +70°C
-40°C to +85°C
PIN-PACKAGE
100 LQFP (14mm)
100 LQFP (14mm)
DS21Q50
100
1
LQFP
Note:
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
www.maxim-ic.com/errata.
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REV: 013004
DS21Q50
TABLE OF CONTENTS
1.
2.
INTRODUCTION ...............................................................................................................................6
PIN DESCRIPTION............................................................................................................................9
2.1
P
IN
F
UNCTION
D
ESCRIPTION
.........................................................................................................15
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
2.1.6
2.1.7
System (Backplane) Interface Pins .......................................................................................................15
Alternate Jitter Attenuator ....................................................................................................................16
Clock Synthesizer..................................................................................................................................16
Parallel Port Control Pins....................................................................................................................16
Serial Port Control Pins .......................................................................................................................17
Line Interface Pins................................................................................................................................18
Supply Pins ...........................................................................................................................................18
3.
HOST INTERFACE PORT..............................................................................................................20
3.1
P
ARALLEL
P
ORT
O
PERATION
........................................................................................................20
3.2
S
ERIAL
P
ORT
O
PERATION
.............................................................................................................20
3.3
R
EGISTER
M
AP
.............................................................................................................................23
CONTROL, ID, AND TEST REGISTERS.....................................................................................24
4.1
P
OWER
-U
P
S
EQUENCE
..................................................................................................................25
4.2
F
RAMER
L
OOPBACK
.....................................................................................................................28
4.3
A
UTOMATIC
A
LARM
G
ENERATION
...............................................................................................29
4.4
R
EMOTE
L
OOPBACK
.....................................................................................................................30
4.5
L
OCAL
L
OOPBACK
........................................................................................................................30
STATUS AND INFORMATION REGISTERS .............................................................................32
5.1
CRC4 S
YNC
C
OUNTER
.................................................................................................................34
ERROR COUNT REGISTERS........................................................................................................39
6.1
BPV
OR
C
ODE
V
IOLATION
C
OUNTER
...........................................................................................39
6.2
CRC4 E
RROR
C
OUNTER
...............................................................................................................40
6.3
E-B
IT
/PRBS B
IT
E
RROR
C
OUNTER
..............................................................................................40
6.4
FAS E
RROR
C
OUNTER
..................................................................................................................41
DS0 MONITORING FUNCTION ...................................................................................................42
PRBS GENERATION AND DETECTION ....................................................................................45
SYSTEM CLOCK INTERFACE.....................................................................................................46
4.
5.
6.
7.
8.
9.
10. TRANSMIT CLOCK SOURCE ......................................................................................................47
11. IDLE CODE INSERTION................................................................................................................48
12. PER-CHANNEL LOOPBACK ........................................................................................................49
13. ELASTIC STORE OPERATION ....................................................................................................49
14. ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION .....................................50
15. USER-CONFIGURABLE OUTPUTS.............................................................................................53
16. LINE INTERFACE UNIT ................................................................................................................56
16.1 R
ECEIVE
C
LOCK AND
D
ATA
R
ECOVERY
.......................................................................................56
16.2 T
ERMINATION
...............................................................................................................................57
16.3 R
ECEIVE
M
ONITOR
M
ODE
............................................................................................................57
16.4 T
RANSMIT
W
AVESHAPING AND
L
INE
D
RIVING
.............................................................................59
16.5 J
ITTER
A
TTENUATORS
..................................................................................................................62
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DS21Q50
17. CMI (CODE MARK INVERSION).................................................................................................64
18. INTERLEAVED PCM BUS OPERATION....................................................................................66
19. FUNCTIONAL TIMING DIAGRAMS...........................................................................................68
19.1 R
ECEIVE
T
IMING
D
IAGRAMS
........................................................................................................68
19.2 T
RANSMIT
T
IMING
D
IAGRAMS
......................................................................................................70
20. OPERATING PARAMETERS ........................................................................................................74
21. AC TIMING PARAMETERS AND DIAGRAMS .........................................................................75
21.1 M
ULTIPLEXED
B
US
AC C
HARACTERISTICS
..................................................................................75
21.2 N
ONMULTIPLEXED
B
US
AC C
HARACTERISTICS
...........................................................................78
21.3 S
ERIAL
P
ORT
................................................................................................................................81
21.4 R
ECEIVE
AC C
HARACTERISTICS
...................................................................................................82
21.5 T
RANSMIT
AC C
HARACTERISTICS
................................................................................................84
21.6 S
PECIAL
M
ODES
AC C
HARACTERISTICS
.......................................................................................86
22. PACKAGE INFORMATION...........................................................................................................87
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DS21Q50
LIST OF FIGURES
Figure 1-1. Block Diagram ............................................................................................................................8
Figure 3-1. Serial Port Operation Mode 1 ...................................................................................................21
Figure 3-2. Serial Port Operation Mode 2 ...................................................................................................21
Figure 3-3. Serial Port Operation Mode 3 ...................................................................................................22
Figure 3-4. Serial Port Operation Mode 4 ...................................................................................................22
Figure 16-1. Typical Monitor Port Application...........................................................................................57
Figure 16-2. External Analog Connections (Basic Configuration) .............................................................60
Figure 16-3. External Analog Connections (Protected Interface) ...............................................................60
Figure 16-4. Transmit Waveform Template................................................................................................61
Figure 16-5. Jitter Tolerance........................................................................................................................63
Figure 16-6. Jitter Attenuation.....................................................................................................................63
Figure 17-1. CMI Coding ............................................................................................................................64
Figure 17-2. CMI Code Violation Example ................................................................................................65
Figure 18-1. IBO Configuration Using Two DS21Q50 Transceivers (Eight E1 Lines) ............................67
Figure 19-1. Receive Frame and Multiframe Timing..................................................................................68
Figure 19-2. Receive Boundary Timing (With Elastic Store Disabled)......................................................68
Figure 19-3. Receive Boundary Timing (With Elastic Store Enabled) .......................................................69
Figure 19-4. Receive Interleave Bus Operation ..........................................................................................69
Figure 19-5. Transmit Frame and Multiframe Timing ................................................................................70
Figure 19-6. Transmit Boundary Timing.....................................................................................................70
Figure 19-7. Transmit Interleave Bus Operation.........................................................................................71
Figure 19-8. Framer Synchronization Flowchart.........................................................................................72
Figure 19-9. Transmit Data Flow ................................................................................................................73
Figure 21-1. Intel Bus Read AC Timing (PBTS = 0) ..................................................................................76
Figure 21-2. Intel Bus Write Timing (PBTS = 0)........................................................................................76
Figure 21-3. Motorola Bus AC Timing (PBTS = 1)....................................................................................77
Figure 21-4. Intel Bus Read Timing (PBTS = 0).........................................................................................79
Figure 21-5. Intel Bus Write Timing (PBTS = 0)........................................................................................79
Figure 21-6. Motorola Bus Read Timing (PBTS = 1) .................................................................................80
Figure 21-7. Motorola Bus Write Timing (PBTS = 1) ................................................................................80
Figure 21-8. Serial Bus Timing (BTS1 = 1, BTS0 = 0) ..............................................................................81
Figure 21-9. Receive AC Timing (Receive Elastic Store Disabled) ...........................................................82
Figure 21-10. Receive AC Timing (Receive Elastic Store Enabled) ..........................................................83
Figure 21-11. Transmit AC Timing (IBO Disabled) ...................................................................................85
Figure 21-12. Transmit AC Timing (IBO Enabled) ....................................................................................85
Figure 21-13. NRZ Input AC Timing..........................................................................................................86
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DS21Q50
LIST OF TABLES
Table 2-1. Pin Assignments (by Function) ....................................................................................................9
Table 2-2. Pin Assignment (by LQFP Pin Number)....................................................................................12
Table 3-1. Bus Mode Select.........................................................................................................................20
Table 3-2. Register Map ..............................................................................................................................23
Table 4-1. Sync/Resync Criteria..................................................................................................................26
Table 5-1. Alarm Criteria ............................................................................................................................34
Table 8-1. Transmit PRBS Mode Select......................................................................................................45
Table 8-2. Receive PRBS Mode Select .......................................................................................................45
Table 9-1. Master Port Selection .................................................................................................................47
Table 9-2. Synthesizer Output Select ..........................................................................................................47
Table 15-1. OUTA and OUTB Function Select ..........................................................................................55
Table 16-1. Receive Monitor Mode Gain....................................................................................................57
Table 16-2. Monitor Mode Settings.............................................................................................................58
Table 16-3. Line Build-Out Select in LICR ................................................................................................59
Table 16-4. Transformer Specifications ......................................................................................................59
Table 18-1. IBO Device Assignment...........................................................................................................66
Table 18-2. IBO System Clock Select.........................................................................................................67
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