AS4C4M16SA-C&I
Revision History
Revision
Rev 1.0
Rev 2.0
Rev 3.0
Rev
4.0
Details
Preliminary datasheet.
Modify some typing errors.
Add AS4C4M16SA-6TCN part.
Add AS4C4M16SA-7B2CN
60-ball package and Part Number.
Date
June 2013
March 2014
March 2015
March 2017
Alliance Memory Inc.
511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc.
reserves the right to change products or specification without notice.
Confidential
- 1 of 56 -
Rev.4.0
March 2017
AS4C4M16SA-C&I
Confidential
Features
Fast access time from clock: 5.4/5.4 ns
Fast clock rate: 166/143 MHz
Fully synchronous operation
Internal pipelined architecture
1M word x 16-bit x 4-bank
Programmable Mode registers
- CAS Latency: 2 or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: Sequential or Interleaved
- Burst stop function
- Optional drive strength control
Operating temperature range
- Commercial (0 ~ 70°C)
- Industrial (-40 ~ 85°C)
Auto Refresh and Self Refresh
4096 refresh cycles/64ms
CKE power down mode
Single +3.3V
0.3V power supply
Interface: LVTTL
54-pin 400 mil plastic TSOP II package
54-ball 8.0 x 8.0 x 1.2mm (max) FBGA
package
60-ball 6.4 x 10.1 x 1.0mm FBGA package
- All parts ROHS Compliant
Table 1. Key Specifications
AS4C4M16S
tCK3
Clock Cycle time(min.)
tAC3
Access time from CLK (max.)
tRAS
Row Active time(min.)
tRC
Row Cycle time(min.)
Table 2.Ordering Information
Part Number
Frequency
AS4C4M16SA-6BIN
166MHz
AS4C4M16SA-7BCN
143MHz
AS4C4M16SA-6TIN
166MHz
AS4C4M16SA-7TCN
143MHz
AS4C4M16SA-6TCN
166MHz
AS4C4M16SA-7B2CN
143MHz
64M – (4M x 16 bit) Synchronous DRAM (SDRAM)
Overview
Advanced (Rev. 3.0, Mar. /2015)
The 64Mb SDRAM is a high-speed CMOS
synchronous DRAM containing 64 Mbits. It is internally
configured as 4 Banks of 1M word x 16 DRAM with a
synchronous interface (all signals are registered on
the positive edge of the clock signal, CLK). Read and
write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of a
Bank Activate command which is then followed by a
Read or Write command.
The SDRAM provides for programmable Read or
Write burst lengths of 1, 2, 4, 8, or full page, with a
burst termination option. An auto precharge function
may be enabled to provide a self-timed row precharge
that is initiated at the end of the burst sequence. The
refresh functions, either Auto or Self Refresh are easy
to use. By having a programmable mode register, the
system can choose the most suitable modes to
maximize its performance. These devices are well
suited for applications requiring high memory
bandwidth and particularly well suited to high
performance PC applications.
-6/7
6/7
5.4/5.4
42/42
60/63
ns
ns
ns
ns
Package
54-Ball FBGA
54-Ball FBGA
54-Pin TSOPII
54-Pin TSOPII
54-Pin TSOPII
60-Ball FBGA
Temperature
Industrial
Commercial
Industrial
Commercial
Commercial
Commercial
Temp Range
-40 ~ 85°C
0 ~ 70°C
-40 ~ 85°C
0 ~ 70°C
0 ~ 70°C
0 ~ 70°C
B: indicates FBGA package
B2: indicates a second FBGA package option
T: indicates TSOP II package N: indicates Pb and Halogen Free
Confidential
- 2 of 56 -
Rev.4.0
March 2017
AS4C4M16SA-C&I
Figure 1. Pin Assignment (Top View)
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM
WE#
CAS#
RAS#
CS#
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
NC/RFU
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS
Figure 1.1
54
Ball Assignment (Top View)
1
A
B
C
D
E
F
G
H
J
VSS
DQ14
DQ12
DQ10
DQ8
UDQM
NC
A8
VSS
2
DQ15
DQ13
DQ11
DQ9
NC
CLK
A11
A7
A5
3
VSSQ
VDDQ
VSSQ
VDDQ
VSS
CKE
A9
A6
A4
…
7
VDDQ
VSSQ
VDDQ
VSSQ
VDD
CAS#
BA0
A0
A3
8
DQ0
DQ2
DQ4
DQ6
LDQM
RAS#
BA1
A1
A2
9
VDD
DQ1
DQ3
DQ5
DQ7
WE#
CS#
A10
VDD
Figure 1.2
60
Ball Assignment (Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
VSS
DQ14
DQ13
DQ12
DQ10
DQ9
DQ8
NC
NC
NC
CKE
A11
A8
A6
VSS
2
DQ15
VSSQ
VDDQ
DQ11
VSSQ
VDDQ
NC
NC
UDQM
CLK
NC
A9
A7
A5
A4
…
6
DQ0
VDDQ
VSSQ
DQ4
VDDQ
VSSQ
NC
NC
LDQM
RAS#
NC
BA1
A0
A2
A3
Rev.4.0
7
VDD
DQ1
DQ2
DQ3
DQ5
DQ6
DQ7
NC
WE#
CAS#
CS#
BA0
A10
A1
VDD
March 2017
Confidential
- 3 of 56 -
AS4C4M16SA-C&I
Figure 2. Block Diagram
CLK
CKE
CS#
RAS#
CAS#
WE#
CLOCK
BUFFER
Row
Decoder
1M x 16
CELL ARRAY
(BANK #A)
Column Decoder
DQ15
LDQM, UDQM
Row
Decoder
A10/AP
COLUMN
COUNTER
MODE
REGISTER
1M x 16
CELL ARRAY
(BANK #B)
Column Decoder
A0
A9
A11
BA0
BA1
ADDRESS
BUFFER
~
REFRESH
COUNTER
Row
Decoder
1M x 16
CELL ARRAY
(BANK #C)
Column Decoder
Row
Decoder
1M x 16
CELL ARRAY
(BANK #D)
Column Decoder
Confidential
- 4 of 56 -
Rev.4.0
~
March 2017
COMMAND
DECODER
CONTROL
SIGNAL
GENERATOR
DQ Buffer
DQ0
AS4C4M16SA-C&I
Pin Descriptions
Table 3. Pin Details
Symbol
CLK
Type
Input
Description
Clock:
CLK is driven by the system clock. All SDRAM input signals are sampled on
the positive edge of CLK. CLK also increments the internal burst counter and
controls the output registers.
Clock Enable:
CKE activates (HIGH) and deactivates (LOW) the CLK signal. If
CKE goes low synchronously with clock (set-up and hold time same as other
inputs), the internal clock is suspended from the next clock cycle and the state of
output and burst address is frozen as long as the CKE remains low. When all
banks are in the idle state, deactivating the clock controls the entry to the Power
Down and Self Refresh modes. CKE is synchronous except after the device enters
Power Down and Self Refresh modes, where CKE becomes asynchronous until
exiting the same mode. The input buffers, including CLK, are disabled during
Power Down and Self Refresh modes, providing low standby power.
Bank Activate:
BA0, BA1 input select the bank for operation.
BA1
0
0
1
1
A0-A11
Input
BA0
0
1
0
1
Select Bank
BANK #A
BANK #B
BANK #C
BANK #D
CKE
Input
BA0,BA1
Input
Address Inputs:
A0-A11 are sampled during the BankActivate command (row
address A0-A11) and Read/Write command (column address A0-A7 with A10
defining Auto Precharge) to select one location out of the 1M available in the
respective bank. During a Precharge command, A10 is sampled to determine if all
banks are to be precharged (A10 = HIGH). The address inputs also provide the op-
code during a Mode Register Set command.
Chip Select:
CS# enables (sampled LOW) and disables (sampled HIGH) the
command decoder. All commands are masked when CS# is sampled HIGH. CS#
provides for external bank selection on systems with multiple banks. It is
considered part of the command code.
Row Address Strobe:
The RAS# signal defines the operation commands in
conjunction with the CAS# and WE# signals and is latched at the positive edges of
CLK. When RAS# and CS# are asserted "LOW" and CAS# is asserted "HIGH,"
either the BankActivate command or the Precharge command is selected by the
WE# signal. When the WE# is asserted "HIGH," the BankActivate command is
selected and the bank designated by BA is turned on to the active state. When the
WE# is asserted "LOW," the Precharge command is selected and the bank
designated by BA is switched to the idle state after the precharge operation.
Column Address Strobe:
The CAS# signal defines the operation commands in
conjunction with the RAS# and WE# signals and is latched at the positive edges of
CLK. When RAS# is held "HIGH" and CS# is asserted "LOW," the column access
is started by asserting CAS# "LOW." Then, the Read or Write command is
selected by asserting WE# "LOW" or "HIGH."
Write Enable:
The WE# signal defines the operation commands in conjunction
with the RAS# and CAS# signals and is latched at the positive edges of CLK. The
WE# input is used to select the BankActivate or Precharge command and Read or
Write command.
CS#
Input
RAS#
Input
CAS#
Input
WE#
Input
Confidential
- 5 of 56 -
Rev.4.0
March 2017
京公网安备 11010802033920号
EEWORLD
