DS21348/DS21Q348
3.3V E1/T1/J1 Line Interface
www.maxim-ic.com
FEATURES
Complete E1, T1, or J1 Line Interface Unit
(LIU)
Supports Both Long-Haul And Short-Haul
Trunks
Internal Software-Selectable Receive-Side
Termination for 75Ω/100Ω/120Ω
3.3V Power Supply
32-Bit or 128-Bit Crystal-Less Jitter
Attenuator Requires Only a 2.048MHz
Master Clock for Both E1 and T1 with
Option to Use 1.544MHz for T1
Generates the Appropriate Line Build-Outs,
with and without Return loss, for E1 and
DSX-1 and CSU Line Build-Outs for T1
AMI, HDB3, and B8ZS, Encoding/Decoding
16.384MHz, 8.192MHz, 4.096MHz, or
2.048MHz Clock Output Synthesized to
Recovered Clock
Programmable Monitor Mode for Receiver
Loopbacks and PRBS Pattern Generation/
Detection with Output for Received Errors
Generates/Detects In-Band Loop Codes,
1 to 16 Bits Including CSU Loop Codes
8-Bit Parallel or Serial Interface with
Optional Hardware Mode
Muxed and Nonmuxed Parallel Bus Supports
Intel or Motorola
Detects/Generates Blue (AIS) Alarms
NRZ/Bipolar Interface for Tx/Rx Data I/O
Transmit Open-Circuit Detection
Receive Carrier Loss (RCL) Indication
(G.775)
High-Impedance State for TTIP and TRING
50mA (RMS) Current Limiter
PIN CONFIGURATIONS
111
TOP VIEW
PRELMINARY
44
1
DS21348
44 TQFP
DS21Q348
49 CSBGA
(7mm x 7mm)
See Section
8
for 144-pin CSBGA pinout.
ORDERING INFORMATION
PART
DS21348TN
DS21348TN+
DS21348T
DS21348T+
DS21348GN
DS21348GN+
DS21348G
DS21348G+
DS21Q348N
DS21Q348
CHANNEL
Single
Single
Single
Single
Single
Single
Single
Single
Four
Four
TEMP
RANGE
-40°C to +85°C
-40°C to +85°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
PIN-PACKAGE
44 TQFP
44 TQFP
44 TQFP
44 TQFP
49 CSBGA
49 CSBGA
49 CSBGA
49 CSBGA
144 CSBGA
144 CSBGA
+
Denotes lead-free/RoHS-compliant package.
Note:
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
www.maxim-ic.com/errata.
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REV: 011206
DS21348/DS21Q348
DETAILED DESCRIPTION
The DS21348 is a complete selectable E1 or T1 line interface unit (LIU) for short-haul and long-haul
applications. Throughout the data sheet, J1 is represented wherever T1 exists. Receive sensitivity adjusts
automatically to the incoming signal and can be programmed for 0dB to 12dB or 0dB to 43dB for E1
applications and 0dB to 30dB or 0dB to 36dB for T1 applications. The device can generate the necessary
G.703 E1 waveshapes in 75Ω or 120Ω applications and DSX-1 line build-outs or CSU line build-outs of
0dB, -7.5dB, -15dB, and -22.5dB for T1 applications. The crystal-less on-board jitter attenuator requires
only a 2.048MHz MCLK for both E1 and T1 applications (with the option of using a 1.544MHz MCLK
in T1 applications). The jitter attenuator FIFO is selectable to either 32 bits or 128 bits in depth and can
be placed in either the transmit or receive data paths. An X 2.048MHz output clock synthesized to RCLK
is available for use as a backplane system clock (where n = 1, 2, 4, or 8).
The DS21348 has diagnostic capabilities such as loopbacks and PRBS pattern generation/detection. 16-
bit loop-up and loop-down codes can be generated and detected. The device can be controlled through an
8-bit parallel muxed or nonmuxed port, serial port, or used in hardware mode. The device fully meets all
of the latest E1 and T1 specifications including ANSI T1.403-1999, ANSI T1.408, AT&T TR 62411,
ITU G.703, G.704, G.706, G.736, G.775, G.823, I.431, O.151, O.161, ETSI ETS 300 166, JTG.703,
JTI.431, JJ-20.1, TBR12, TBR13, and CTR4.
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DS21348/DS21Q348
TABLE OF CONTENTS
1.
2.
3.
INTRODUCTION.................................................................................................................. 6
1.1
2.1
3.1
3.2
3.3
DOCUMENT REVISION HISTORY...............................................................................................6
P
IN
D
ESCRIPTIONS
........................................................................................................................14
R
EGISTER
M
AP
.............................................................................................................................25
P
ARALLEL
P
ORT
O
PERATION
.........................................................................................................26
S
ERIAL
P
ORT
O
PERATION
..............................................................................................................26
D
EVICE
P
OWER
-U
P AND
R
ESET
.....................................................................................................32
PIN DESCRIPTION............................................................................................................ 10
HARDWARE MODE .......................................................................................................... 25
4.
5.
6.
CONTROL REGISTERS .................................................................................................... 29
4.1
STATUS REGISTERS ....................................................................................................... 36
DIAGNOSTICS .................................................................................................................. 41
6.1
6.2
I
N
-B
AND
L
OOP
C
ODE
G
ENERATION AND
D
ETECTION
......................................................................41
L
OOPBACKS
..................................................................................................................................46
Remote Loopback (RLB) ..................................................................................................................... 46
Local Loopback (LLB) .......................................................................................................................... 46
Analog Loopback (ALB) ....................................................................................................................... 46
Dual Loopback (DLB)........................................................................................................................... 46
6.2.1
6.2.2
6.2.3
6.2.4
6.3
6.4
6.5
PRBS G
ENERATION AND
D
ETECTION
............................................................................................47
E
RROR
C
OUNTER
..........................................................................................................................47
Error Counter Update........................................................................................................................... 48
6.4.1
E
RROR
I
NSERTION
........................................................................................................................48
R
ECEIVER
.....................................................................................................................................49
T
RANSMITTER
...............................................................................................................................50
J
ITTER
A
TTENUATOR
.....................................................................................................................50
G.703 S
YNCHRONIZATION
S
IGNAL
.................................................................................................51
7.
ANALOG INTERFACE ...................................................................................................... 49
7.1
7.2
7.3
7.4
8.
9.
10.
11.
12.
DS21Q348 QUAD LIU ....................................................................................................... 58
DC CHARACTERISTICS ................................................................................................... 62
THERMAL CHARACTERISTICS....................................................................................... 63
AC CHARACTERISTICS ................................................................................................... 64
PACKAGE INFORMATION ............................................................................................... 73
12.1 44-P
IN
TQFP (56-G4012-001) .....................................................................................................73
12.2 49-B
ALL
CSGBA (7
MM X
7
MM
) (56-G6006-001) ...........................................................................74
12.3 144-B
ALL
CSBGA (17
MM X
17
MM
) (56-G6011-001) .....................................................................75
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DS21348/DS21Q348
LIST OF FIGURES
Figure 1-1. DS21348 Block Diagram ..........................................................................................................7
Figure 1-2. Receive Logic...........................................................................................................................8
Figure 1-3. Transmit Logic..........................................................................................................................9
Figure 2-1. Parallel Port Mode Pinout (BIS1 = 0, BIS0 = 1 or 0) (TQFP Package) ..................................22
Figure 2-2. Serial Port Mode Pinout (BIS1 = 1, BIS0 = 0) (TQFP Package) ............................................23
Figure 2-3. Hardware Mode Pinout (BIS1 = 1, BIS0 = 1) (TQFP Package) .............................................24
Figure 3-1. Serial Port Operation for Read Access (R = 1) Mode 1 .........................................................27
Figure 3-2. Serial Port Operation for Read Access Mode 2 .....................................................................27
Figure 3-3. Serial Port Operation for Read Access Mode 3 .....................................................................27
Figure 3-4. Serial Port Operation for Read Access Mode 4 .....................................................................28
Figure 3-5. Serial Port Operation for Write Access (R = 0) Modes 1 and 2..............................................28
Figure 3-6. Serial Port Operation for Write Access (R = 0) Modes 3 and 4..............................................28
Figure 7-1. Basic Interface .......................................................................................................................52
Figure 7-2. Protected Interface Using Internal Receive Termination........................................................53
Figure 7-3. Protected Interface Using External Receive Termination.......................................................54
Figure 7-4. E1 Transmit Pulse Template ..................................................................................................55
Figure 7-5. T1 Transmit Pulse Template ..................................................................................................56
Figure 7-6. Jitter Tolerance ......................................................................................................................57
Figure 7-7. Jitter Attenuation ....................................................................................................................57
Figure 8-1. 144-CSBGA (17mm x 17mm) Pinout .....................................................................................61
Figure 11-1. Intel Bus Read Timing (PBTS = 0, BIS1 = 0, BIS0 = 0) .......................................................65
Figure 11-2. Intel Bus Write Timing (PBTS = 0, BIS1 = 0, BIS0 = 0) .......................................................65
Figure 11-3. Motorola Bus Timing (PBTS = 1, BIS1 = 0, BIS0 = 0)..........................................................66
Figure 11-4. Intel Bus Read Timing (PBTS = 0, BIS1 = 0, BIS0 = 1) .......................................................68
Figure 11-5. Intel Bus Write Timing (PBTS = 0, BIS1 = 0, BIS0 = 1) .......................................................68
Figure 11-6. Motorola Bus Read Timing (PBTS = 1, BIS1 = 0, BIS0 = 1) ................................................69
Figure 11-7. Motorola Bus Write Timing (PBTS = 1, BIS1 = 0, BIS0 = 1) ................................................69
Figure 11-8. Serial Bus Timing (BIS1 = 1, BIS0 = 0) ................................................................................70
Figure 11-9. Receive Side Timing ............................................................................................................71
Figure 11-10. Transmit Side Timing .........................................................................................................72
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DS21348/DS21Q348
LIST OF TABLES
Table 2-1. Bus Interface Selection ...........................................................................................................10
Table 2-2. Pin Assignment in Parallel Port Mode .....................................................................................10
Table 2-3. Pin Assignment in Serial Port Mode ........................................................................................11
Table 2-4. Pin Assignment in Hardware Mode .........................................................................................12
Table 2-5. Pin Descriptions in Parallel Port Mode (Sorted by Pin Name, DS21348T Pin Numbering).....14
Table 2-6. Pin Descriptions in Serial Port Mode (Sorted By Pin Name, DS21348T Pin Numbering) .......16
Table 2-7. Pin Descriptions in Hardware Mode (Sorted By Pin Name, DS21348T Pin Numbering) ........18
Table 2-8. Loopback Control in Hardware Mode ......................................................................................21
Table 2-9. Transmit Data Control in Hardware Mode ...............................................................................21
Table 2-10. Receive Sensitivity Settings ..................................................................................................21
Table 2-11. Monitor Gain Settings ............................................................................................................21
Table 2-12. Internal Rx Termination Select ..............................................................................................21
Table 2-13. MCLK Selection.....................................................................................................................22
Table 3-1. Register Map ...........................................................................................................................25
Table 4-1. MCLK Selection.......................................................................................................................30
Table 4-2. Receive Equalizer Sensitivity Settings ....................................................................................32
Table 4-3. Backplane Clock Select...........................................................................................................34
Table 4-4. Monitor Gain Settings ..............................................................................................................34
Table 4-5. Internal Rx Termination Select ................................................................................................34
Table 5-1. Received Alarm Criteria ..........................................................................................................36
Table 5-2. Receive Level Indication .........................................................................................................40
Table 6-1. Transmit Code Length .............................................................................................................41
Table 6-2. Receive Code Length..............................................................................................................42
Table 6-3. Definition of Received Errors...................................................................................................47
Table 6-4. Function of ECRS Bits and RNEG Pin ....................................................................................48
Table 7-1. Line Build-Out Select for E1 in Register CCR4 (ETS = 0).......................................................51
Table 7-2. Line Build-Out Select for T1 in Register CCR4 (ETS = 1).......................................................51
Table 7-3. Transformer Specifications for 3.3V Operation .......................................................................51
Table 8-1. DS21Q348 Pin Assignment.....................................................................................................58
Table 9-1. Recommended DC Operating Conditions ...............................................................................62
Table 9-2. Capacitance ............................................................................................................................62
Table 9-3. DC Characteristics ..................................................................................................................62
Table 10-1. Thermal Characteristics—DS21Q348 CSBGA Package.......................................................63
Table 10-2. Theta-JA (θ
JA
) vs. Airflow.......................................................................................................63
Table 11-1. AC Characteristics—Multiplexed Parallel Port (BIS1 = 0, BIS0 = 0) .....................................64
Table 11-2. AC Characteristics—Nonmultiplexed Parallel Port (BIS1 = 0, BIS0 = 1)...............................67
Table 11-3. AC Characteristics—Serial Port (BIS1 = 1, BIS0 = 0) ...........................................................70
Table 11-4. AC Characteristics—Receive Side ........................................................................................71
Table 11-5. AC Characteristics—Transmit Side .......................................................................................72
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