This product is not recommended for new designs.
TOP221-227
TOPSwitch-II
Family
Three-Terminal Off-Line PWM Switch
Product Highlights
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Lowest cost, lowest component count switcher solution
Cost competitive with linears above 5 W
Very low AC/DC losses – up to 90% efficiency
Built-in Auto-restart and Current limiting
Latching Thermal shutdown for system level protection
Implements Flyback, Forward, Boost or Buck topology
Works with primary or opto feedback
Stable in discontinuous or continuous conduction mode
Source connected tab for low EMI
Circuit simplicity and Design Tools reduce time to market
AC
IN
D
CONTROL
TOPSwitch
S
C
Description
The second generation TOPSwitch™-II family is more cost
effective and provides several enhancements over the first
generation TOPSwitch family. The TOPSwitch-II family
extends the power range from 100W to 150W for 100/115/
230 VAC input and from 50W to 90W for 85-265 VAC univer-
sal input. This brings TOPSwitch technology advantages
to many new applications, i.e. TV, Monitor, Audio amplifiers,
etc. Many significant circuit enhancements that reduce the
sensitivity to board layout and line transients now make the
design even easier. The standard 8L PDIP package option
Figure 1. Typical Flyback Application.
PI-1951-091996
reduces cost in lower power, high efficiency applications.
The internal lead frame of this package uses six of its pins to
transfer heat from the chip directly to the board, eliminating
the cost of a heat sink. TOPSwitch incorporates all functions
necessary for a switched mode control system into a three
terminal monolithic IC: power MOSFET, PWM controller, high
voltage start up circuit, loop compensation and fault protec-
tion circuitry.
Output Power Table
TO-220 (Y) Package
1
PART
ORDER
NUMBER
TOP221YN
TOP222YN
TOP223YN
TOP224YN
TOP225YN
TOP226YN
TOP227YN
Single Voltage Input
3
100/115/230 VAC ±15%
Wide Range Input
85 to 265 VAC
PART
ORDER
NUMBER
8L PDIP (P) or 8L SMD (G) Package
2
Single Voltage Input
3
100/115/230 VAC ±15%
Wide Range Input
85 to 265 VAC
P
MAX4,6
12 W
25 W
50 W
75 W
100 W
125 W
150 W
P
MAX4,6
7W
15 W
30 W
45 W
60 W
75 W
90 W
P
MAX5,6
9W
15 W
25 W
30 W
P
MAX5,6
6W
10 W
15 W
20 W
TOP221PN or TOP221GN
TOP222PN or TOP222GN
TOP223PN or TOP223GN
TOP224PN or TOP224GN
Notes:
1.
Package outline: TO-220/3
2.
Package Outline: DIP-8 or SMD-8
3.
100/115 VAC with doubler input
4.
Assumes appro-
priate heat sinking to keep the maximum TOPSwitch junction temperature below 100
°C.
5.
Soldered to 1 sq. in. (6.45 cm
2
), 2 oz.
copper clad (610 gm/m
2
)
6.
P
MAX
is the maximum practical continuous power output level for conditions shown. The continuous
power capability in a given application depends on thermal environment, transformer design, efficiency required, minimum spec-
ified input voltage, input storage capacitance, etc.
7.
Refer to key application considerations section when using TOPSwitch-II in
an existing TOPSwitch design.
www.power.com
August 2016
This Product is Covered by Patents and/or Pending Patent Applications.
TOP221-227
CONTROL
ZC
VC
0
INTERNAL
SUPPLY
DRAIN
SHUNT REGULATOR/
ERROR AMPLIFIER
-
+
5.7 V
5.7 V
4.7 V
SHUTDOWN/
AUTO-RESTART
1
+
-
∏
8
+
-
IFB
VI
LIMIT
THERMAL
SHUTDOWN
S
Q
Q
POWER-UP
RESET
R
OSCILLATOR
DMAX
CLOCK
SAW
CONTROLLED
TURN-ON
GATE
DRIVER
-
+
PWM
COMPARATOR
S
R
Q
Q
LEADING
EDGE
BLANKING
MINIMUM
ON-TIME
DELAY
RE
SOURCE
PI-1935-091696
Figure 2. Functional Block Diagram.
Pin Functional Description
DRAIN Pin:
Output MOSFET drain connection. Provides internal bias
current during start-up operation via an internal switched
high-voltage current source. Internal current sense point.
CONTROL Pin:
Error amplifier and feedback current input pin for duty cycle
control. Internal shunt regulator connection to provide inter-
nal bias current during normal operation. It is also used as
the connection point for the supply bypass and auto-restart/
compensation capacitor.
SOURCE Pin:
YN package – Output MOSFET source connection for high
voltage power return. Primary side circuit
common and reference point.
PN and GN package – Primary-side control circuit common
and reference point.
SOURCE (HV RTN) Pin: (P and G package only)
Output MOSFET source connection for high voltage power
return.
2
Rev. G 08/16
Tab Internally
Connected to SOURCE Pin
DRAIN
SOURCE
CONTROL
Y Package (TO-220/3)
S
S
S
C
1
2
2
4
8
7
6
5
S (HV RTN)
S (HV RTN)
S (HV RTN)
D
P Package (DIP-8)
G Package (SMD-8)
PI-2084-040401
Figure 3. Pin Configuration.
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TOP221-227
TOPSwitch-II Family Functional Description
TOPSwitch is a self biased and protected linear control cur-
rent-to-duty cycle converter with an open drain output. High
efficiency is achieved through the use of CMOS and integra-
tion of the maximum number of functions possible. CMOS
process significantly reduces bias currents as compared to
bipolar or discrete solutions. Integration eliminates external
power resistors used for current sensing and/or supplying
initial start-up bias current.
During normal operation, the duty cycle of the internal output
MOSFET decreases linearly with increasing CONTROL pin
current as shown in Figure 4. To implement all the required
control, bias, and protection functions, the DRAIN and CON-
TROL pins each perform several functions as described
below. Refer to Figure 2 for a block diagram and to Figure 6
for timing and voltage waveforms of the TOPSwitch inte-
grated circuit.
Auto-restart
DMAX
IB
Slope = PWM Gain
Duty Cycle (%)
DMIN
ICD1 2.0
6.0
IC (mA)
PI-2040-050197
Figure 4. Relationship of Duty Cycle to CONTROL Pin Current.
VC
5.7 V
4.7 V
0
VIN
0
DRAIN
VC
5.7 V
4.7 V
0
DRAIN
VIN
0
C
T
is the total external capacitance
connected to the CONTROL pin
Figure 5. Start-up Waveforms for (a) Normal Operation and (b) Auto-restart.
3
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Rev. G 08/16
TOP221-227
TOPSwitch-II Family Functional Description (cont.)
Control Voltage Supply
CONTROL pin voltage V
C
is the supply or bias voltage for the
controller and driver circuitry. An external bypass capacitor
closely connected between the CONTROL and SOURCE
pins is required to supply the gate drive current. The total
amount of capacitance connected to this pin (C
T
) also sets
the auto-restart timing as well as control loop compensation.
V
C
is regulated in either of two modes of operation. Hyster-
etic regulation is used for initial start-up and overload opera-
tion. Shunt regulation is used to separate the duty cycle
error signal from the control circuit supply current. During
start-up, CONTROL pin current is supplied from a high-volt-
age switched current source connected internally between
the DRAIN and CONTROL pins. The current source pro-
vides sufficient current to supply the control circuitry as well
as charge the total external capacitance (C
T
).
The first time V
C
reaches the upper threshold, the high-
voltage current source is turned off and the PWM modulator
and output transistor are activated, as shown in Figure 5(a).
During normal operation (when the output voltage is regulat-
ed) feedback control current supplies the V
C
supply current.
The shunt regulator keeps V
C
at typically 5.7 V by shunting
CONTROL pin feedback current exceeding the required DC
supply current through the PWM error signal sense resistor
R
E
. The low dynamic impedance of this pin (Z
C
) sets the
gain of the error amplifier when used in a primary feedback
configuration. The dynamic impedance of the CONTROL
pin together with the external resistance and capacitance
determines the control loop compensation of the power
system.
If the CONTROL pin total external capacitance (C
T
) should
discharge to the lower threshold, the output MOSFET is
turned off and the control circuit is placed in a low-current
standby mode. The high-voltage current source turns on
and charges the external capacitance again. Charging
current is shown with a negative polarity and discharging
current is shown with a positive polarity in Figure 6. The
hysteretic auto-restart comparator keeps V
C
within a window
of typically 4.7 to 5.7 V by turning the high-voltage current
source on and off as shown in Figure 5(b). The auto-restart
circuit has a divide-by-8 counter which prevents the output
MOSFET from turning on again until eight discharge-charge
cycles have elapsed. The counter effectively limits
TOPSwitch power dissipation by reducing the auto-restart
duty cycle to typically 5%. Auto-restart continues to cycle
until output voltage regulation is again achieved.
Bandgap Reference
All critical TOPSwitch internal voltages are derived from a
temperature-compensated bandgap reference. This refer-
ence is also used to generate a temperature-compensated
current source which is trimmed to accurately set the oscilla-
tor frequency and MOSFET gate drive current.
Oscillator
The internal oscillator linearly charges and discharges the
internal capacitance between two voltage levels to create a
sawtooth waveform for the pulse width modulator. The oscil-
lator sets the pulse width modulator/current limit latch at the
beginning of each cycle. The nominal frequency of 100 kHz
was chosen to minimize EMI and maximize efficiency in
power supply applications. Trimming of the current reference
improves the frequency accuracy.
Pulse Width Modulator
The pulse width modulator implements a voltage-mode
control loop by driving the output MOSFET with a duty cycle
inversely proportional to the current into the CONTROL pin
which generates a voltage error signal across R
E
. The error
signal across R
E
is filtered by an RC network with a typical
corner frequency of 7 kHz to reduce the effect of switching
noise. The filtered error signal is compared with the internal
oscillator sawtooth waveform to generate the duty cycle
waveform. As the control current increases, the duty cycle
decreases. A clock signal from the oscillator sets a latch
which turns on the output MOSFET. The pulse width modu-
lator resets the latch, turning off the output MOSFET. The
maximum duty cycle is set by the symmetry of the internal
oscillator. The modulator has a minimum ON-time to keep
the current consumption of the TOPSwitch independent
of the error signal. Note that a minimum current must be
driven into the CONTROL pin before the duty cycle begins to
change.
Gate Driver
The gate driver is designed to turn the output MOSFET on at
a controlled rate to minimize common-mode EMI. The gate
drive current is trimmed for improved accuracy.
Error Amplifier
The shunt regulator can also perform the function of an er-
ror amplifier in primary feedback applications. The shunt
regulator voltage is accurately derived from the temperature
compensated bandgap reference. The gain of the error
amplifier is set by the CONTROL pin dynamic impedance.
The CONTROL pin clamps external circuit signals to the V
C
voltage level. The CONTROL pin current in excess of the
supply current is separated by the shunt regulator and flows
through R
E
as a voltage error signal.
Cycle-By-Cycle Current Limit
The cycle by cycle peak drain current limit circuit uses the
output MOSFET ON-resistance as a sense resistor. A current
limit comparator compares the output MOSFET ON-state
drain-source voltage, V
DS(ON)
with a threshold voltage. High
drain current causes V
DS(ON)
to exceed the threshold voltage
and turns the output MOSFET off until the start of the next
clock cycle. The current limit comparator threshold voltage
is temperature compensated to minimize variation of the
effective peak current limit due to temperature related
changes in output MOSFET R
DS(ON)
.
4
Rev. G 08/16
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TOP221-227
VIN
VIN
0
DRAIN
VOUT
0
IOUT
0
VC
• • •
0
• • •
VC(reset)
IC
0
• • •
• • •
Figure 6. Typical Waveforms for (1) Normal Operation, (2) Auto-restart, and (3) Power Down Reset.
The leading edge blanking circuit inhibits the current limit
comparator for a short time after the output MOSFET is
turned on. The leading edge blanking time has been set so
that current spikes caused by primary-side capacitances
and secondary-side rectifier reverse recovery time will not
cause premature termination of the switching pulse.
The current limit can be lower for a short period after the
leading edge blanking time as shown in Figure 12. This is
due to dynamic characteristics of the MOSFET. To avoid trig-
gering the current limit in normal operation, the drain current
waveform should stay within the envelope shown.
Shutdown/Auto-restart
To minimize TOPSwitch power dissipation, the shutdown/
auto-restart circuit turns the power supply on and off at an
auto-restart duty cycle of typically 5% if an out of regulation
condition persists. Loss of regulation interrupts the external
current into the CONTROL pin. V
C
regulation changes from
shunt mode to the hysteretic auto-restart mode described
above. When the fault condition is removed, the power sup-
ply output becomes regulated, V
C
regulation returns to shunt
mode, and normal operation of the power supply resumes.
Overtemperature Protection
Temperature protection is provided by a precision analog
circuit that turns the output MOSFET off when the junction
temperature exceeds the thermal shutdown temperature
(typically 135 °C). Activating the power-up reset circuit by
removing and restoring input power or momentarily pulling
the CONTROL pin below the power-up reset threshold resets
the latch and allows TOPSwitch to resume normal power
supply operation. V
C
is regulated in hysteretic mode and a
4.7 V to 5.7 V (typical) sawtooth waveform is present on the
CONTROL pin when the power supply is latched off.
High-Voltage Bias Current Source
This current source biases TOPSwitch from the DRAIN pin
and charges the CONTROL pin external capacitance (C
T
)
during start-up or hysteretic operation. Hysteretic opera-
tion occurs during auto-restart and overtemperature latched
shutdown. The current source is switched on and off with an
effective duty cycle of approximately 35%. This duty cycle
is determined by the ratio of CONTROL pin charge (I
C
) and
discharge currents (I
CD1
and I
CD2
). This current source is
turned off during normal operation when the output MOSFET
is switching.
5
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Rev. G 08/16
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