PHP78NQ03LT
N-channel TrenchMOS logic level FET
Rev. 06 — 30 January 2009
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industrial applications only.
1.2 Features and benefits
Suitable for high frequency
applications due to fast switching
characteristics
Suitable for logic level gate drive
sources
1.3 Applications
Computer motherboards
DC-to-DC convertors
1.4 Quick reference data
Table 1.
V
DS
I
D
P
tot
Quick reference
Conditions
V
GS
= 10 V; T
mb
= 25 °C
T
mb
= 25 °C; see
Figure 2
Min
-
-
-
Typ
-
-
-
Max
25
75
93
Unit
V
A
W
drain-source voltage T
j
≥
25 °C; T
j
≤
175 °C
drain current
total power
dissipation
gate-drain charge
Symbol Parameter
Dynamic characteristics
Q
GD
V
GS
= 5 V; I
D
= 50 A;
V
DS
= 15 V; T
j
= 25 °C;
see
Figure 11
V
GS
= 10 V; I
D
= 25 A;
T
j
= 25 °C; see
Figure 9;
see
Figure 10
-
4.2
5.6
nC
Static characteristics
R
DSon
drain-source
on-state resistance
-
7.65
9
mΩ
NXP Semiconductors
PHP78NQ03LT
N-channel TrenchMOS logic level FET
2. Pinning information
Table 2.
Pin
1
2
3
mb
Pinning information
Symbol
G
D
S
D
Description
gate
drain
source
mounting base; connected to
drain
mb
D
Simplified outline
Graphic symbol
G
mbb076
S
1 2 3
SOT78
(TO-220AB; SC-46)
3. Ordering information
Table 3.
Ordering information
Type number
Package
Name
Description
Version
PHP78NQ03LT
TO-220AB;
plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead SOT78
SC-46
TO-220AB
PHP78NQ03LT_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 30 January 2009
2 of 13
NXP Semiconductors
PHP78NQ03LT
N-channel TrenchMOS logic level FET
4. Limiting values
Table 4.
Symbol
V
DS
V
DGR
V
GS
I
D
Limiting values
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
V
GS
= 5 V; T
mb
= 100 °C; see
Figure 1
V
GS
= 10 V; T
mb
= 25 °C
V
GS
= 10 V; T
mb
= 100 °C
V
GS
= 5 V; T
mb
= 25 °C; see
Figure 1;
see
Figure 3
I
DM
P
tot
T
stg
T
j
I
S
I
SM
E
DS(AL)S
peak drain current
total power dissipation
storage temperature
junction temperature
source current
peak source current
T
mb
= 25 °C
t
p
≤
10 µs; pulsed; T
mb
= 25 °C
t
p
≤
10 µs; pulsed; T
mb
= 25 °C;
see
Figure 3
T
mb
= 25 °C; see
Figure 2
Conditions
T
j
≥
25 °C; T
j
≤
175 °C
T
j
≥
25 °C; T
j
≤
175 °C; R
GS
= 20 kΩ
Min
-
-
-20
-
-
-
-
-
-
-55
-55
-
-
-
Max
25
25
20
43
75
53
61
228
93
175
175
75
228
185
Unit
V
V
V
A
A
A
A
A
W
°C
°C
A
A
mJ
In accordance with the Absolute Maximum Rating System (IEC 60134).
Source-drain diode
Avalanche ruggedness
non-repetitive
V
GS
= 10 V; T
j(init)
= 25 °C; I
D
= 43 A; V
sup
≤
25 V;
drain-source avalanche unclamped; t
p
= 0.25 ms; R
GS
= 50
Ω
energy
PHP78NQ03LT_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 30 January 2009
3 of 13
NXP Semiconductors
PHP78NQ03LT
N-channel TrenchMOS logic level FET
120
I
der
(%)
80
03aa24
120
P
der
(%)
80
03aa16
40
40
0
0
50
100
150
T
mb
(°C)
200
0
0
50
100
150
T
mb
(°C)
200
Fig 1.
Normalized continuous drain current as a
function of mounting base temperature
Fig 2.
Normalized total power dissipation as a
function of mounting base temperature
003aaa175
10
3
I
D
(A)
10
2
100
μ
s
Limit R
DSon
= V
DS
/ I
D
t
p
= 10
μ
s
10
DC
1 ms
10 ms
100 ms
1
1
10
V
DS
(V)
10
2
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PHP78NQ03LT_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 30 January 2009
4 of 13
NXP Semiconductors
PHP78NQ03LT
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 5.
Symbol
R
th(j-a)
R
th(j-mb)
Thermal characteristics
Parameter
Conditions
Min
-
-
Typ
60
-
Max
-
1.6
Unit
K/W
K/W
thermal resistance from vertical in still air
junction to ambient
thermal resistance from see
Figure 4
junction to mounting
base
10
Z
th(j-mb)
(K/W)
1
003aaa233
δ
= 0.5
0.2
0.1
t
p
T
10
-1
0.05
0.02
single pulse
P
δ
=
t
p
t
T
10
-2
10
-5
10
-4
10
-3
10
-2
10
-1
1
t
p
(s)
10
Fig 4.
Transient thermal impedance from junction to mounting base as a function of pulse duration
PHP78NQ03LT_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 30 January 2009
5 of 13
Analog electronics
京公网安备 11010802033920号
EEWORLD
