PI2EQX4402
2.5Gbps x2 Lane Serial PCI Express Repeater/Equalizer
Features
•
•
•
•
•
•
•
•
•
•
Two High Speed PCI Express lanes
Supports PCI Express data rates (2.5 Gbps) on each lane
Adjustable Transmiter De-Emphasis & Amplitude
Adjustable Receiver Equalization
Two Spread Spectrum Reference Clock Buffer Outputs
100Ω Differential CML I/O’s
Low Power (100mW per Channel)
Standby Mode – Power Down State
V
DD
Operating Range: 1.8V +/-0.1V
Packaging (Pb-free & Green):
- 84-ball LFBGA
Description
Pericom Semiconductor’s PI2EQX4402 is a low power, PCI
Express compliant signal re-driver. The device provides
programmable equalization, amplification, and de-emphasis
by using 7 select bits, SEL[0:6], to optimize performance
over a variety of physical mediums by reducing Inter-symbol
interference. PI2EQX4402 supports four 100 Differential CML
data I/O’s between the Protocol ASIC to a switch fabric, across
a backplane, or extends the signals across other distant data
pathways on the user’s platform.
The integrated equalization circuitry provides flexibility with
signal integrity of the PCI Express signal before the re-driver.
Whereas the integrated de-emphasis circuitry provides flexibility
with signal integrity of the PCI Express signal after the re-driver.
In addition to providing signal re-conditioning, Pericom’s
PI2EQX4402 also provides power management Stand-by mode
operated by a Bus Enable pin.
Block Diagram
Pin Description (Top View)
½
½
½½
½
½½
½
½½½½½½
½
½
½
½
½½½½½½
½
½½½½½½
½
½½½½
½½
½½½½
½½½½½½ ½½½½½½ ½½½½½½
½½½
½½½
½½½
½½½½½½½½½
½½½½½½½½
½½½
½½½
½
½½½
½½½
½½
½½½
½½½
½½½½½½ ½½½½½½ ½½½½½½ ½½½½½½
½½½
½½½
½½½½
½½½
½½½
½
½½
½½½½½½ ½½½½½½ ½½½½½½
½½½½½½
½½½½
½½½
½½½
½
½½½
½½½
½½½
½½½
½½½
½½½½½½½½½½½½½
½½½
½½½
½½½
½½½
½½½½½½½½½
½½½½
½½½½½½
½½½½½½½½½½
½½½½½½½½½½½ ½½½½½½½½½½½
½
½½½
½½½
½½½
½½½
½
½½½
½½½
½½½
½½½
½½½
½½½
½½½
½½½
½½½
½½½½½½½½½½½½½½½½½½½½½½
½
½½½½½½
½½½½½½
½½½½½
½½½½½
½½½½½½
½½½½½½
½½½½
½½½½½
½½½½½
½½½½½
½½½½½
½
½½½
½½½½½½
½½½
½½½
½½½½½
½½½½½
½½½
½½½
½½½½½½
½½½
½
½½½
½½½½½½
½½½
½½½½½½ ½½½½½½ ½½½½½½
½½½½
½½½
½½½½½½
½½½
½
½½½½½½ ½½½½½½ ½½½½½½ ½½½½½½
½½½½½ ½½½½½ ½½½½½ ½½½½½ ½½½½½½ ½½½½½½
1
PS8778E
02/15/06
PI2EQX4402
2.5Gbps x2 Lane Serial PCI Express Repeater / Equalizer
Pin Description
Pin #
B1, F1, D2, E2,
B3, F3, H4, B8,
F8, B10, F10
C3
D3
E1, J1, F2, E3, J3,
H7, E8, J8, D9,
E9, F9, E10, J10
C8
D8
G3
H3
G8
H8
A3, B4, B5
A4, C4, C5
G2, J2, J4
H2, K2, J5
B6, A5
C6, A6
K3, K4
J6, J9
B7, A7
C7, A8
K9, G9
K10, H9
C10
D10
C1
D1
G10
H10
G1
H1
A9, A10, B9, C9
Pin Name
V
DD
AI+
AI-
GND
BI+
BI-
CI+
CI-
DI+
DI-
SEL[0:2]_A
SEL[0:2]_B
SEL[0:2]_C
SEL[0:2]_D
SEL[3:4]_A
SEL[3:4]_B
SEL[3:4]_C
SEL[3:4]_D
SEL[5:6]_A
SEL[5:6]_B
SEL[5:6]_C
SEL[5:6]_D
AO+
AO-
BO+
BO-
CO+
CO-
DO+
DO-
EN_
[A,B,C,D]
I/O
PWR
I
I
PWR
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
O
O
O
I
1.8V Supply Voltage
Positive CML Input Channel A with internal 50Ω pull down
Negative CML Input Channel A with internal 50Ω pull down
Supply Ground
Positive CML Input Channel B with internal 50Ω pull down
Negative CML Input Channel B with internal 50Ω pull down
Positive CML Input Channel C with internal 50Ω pull down
Negative CML Input Channel C with internal 50Ω pull down
Positive CML Input Channel D with internal 50Ω pull down
Negative CML Input Channel D with internal 50Ω pull down
Selection pins for equalizer (see Amplifier Configuration Table)
w/ 50KΩ internal pull up
Description
Selection pins for amplifier (see Amplifier Configuration Table)
w/ 50KΩ internal pull up
Selection pins for De-Emphasis (See De-Emphasis Configuration Table)
w/ 50KΩ internal pull up
Positive CML Output Channel A internal 50Ω pull up during normal operation and
2KΩ pull up otherwise.
Negative CML Output Channel A with internal 50Ω pull up during normal opera-
tion and 2KΩ pull up otherwise.
Positive CML Output Channel B with internal 50Ω pull up during normal opera-
tion and 2KΩ pull up otherwise.
Negative CMLOutput Channel B with internal 50Ω pull up during normal opera-
tion and 2KΩ pull up otherwise.
Positive CMLOutput Channel C with internal 50Ω pull up during normal operation
and 2KΩ pull up otherwise.
Negative CMLOutput Channel C with internal 50Ω pull up during normal opera-
tion and 2KΩ pull up otherwise.
Positive CMLOutput Channel D with internal 50Ω pull up during normal operation
and 2KΩ pull up otherwise.
Negative CMLOutput Channel D with internal 50Ω pull up during normal opera-
tion and 2KΩ pull up otherwise.
EN_[A:D] is the enable pin with internal 50KΩ pull up resistor. A LVCMOS high
provides normal operation. A LVCMOS low selects a low power down mode.
2
PS8778E
02/15/06
PI2EQX4402
2.5Gbps x2 Lane Serial PCI Express Repeater / Equalizer
Pin Description
(Continued)
Pin #
H6
H5
K5, K6
K7, K8
J7
K1
A1, A2, B2, C2
Inputs
EN_[A, B, C, D]
High
Low
Pin Name
CKIN-
CKIN+
OUT0+,
OUT0-
OUT1+,
OUT1-
IREF
EN_CLK
NC
I/O
I
I
O
Differential Reference Clock Output
O
O
I
N/A
External 475Ω resistor connection to set the differential output current
Enable output clock pin with internal 50KΩ pull up resistor
No connect pins. For normal operation, leave pins floating
Inputs
EN_CLK
High
Low
Description
Differential Input Reference Clock
Outputs
O+ / O-
Normal output
No output
Clock Outputs
Clock output
No clock output
Maximum Ratings
(Above which useful life may be impaired. For user guidelines, not tested.)
Storage Temperature........................................................ –65°C to +150°C
Supply Voltage to Ground Potential ................................... –0.5V to +2.5V
DC SIG Voltage..........................................................–0.5V to V
DD
+0.5V
Current Output ................................................................-25mA to +25mA
Power Dissipation Continous ......................................................... 800mW
Operating Temperature.............................................................. 0 to +70°C
Note:
Stresses greater than those listed under MAXIMUM RAT-
INGS may cause permanent damage to the device. This is
a stress rating only and functional operation of the device
at these or any other conditions above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for ex-
tended periods may affect reliability.
Output Swing Control
SEL3_[A:D]
0
0
1
1
SEL4_[A:D]
0
1
0
1
Swing
1x
0.8x
1.2x
1.4x
Output De-emphasis Adjustment
SEL5_[A:D]
0
0
1
1
SEL6_[A:D]
0
1
0
1
De-emphasis
0dB
-2.5dB
-3.5dB
-4.5dB
Equalizer Selection
SEL0_[A:D]
0
0
0
0
1
1
1
1
SEL1_[A:D]
0
0
1
1
0
0
1
1
SEL2_[A:D]
0
1
0
1
0
1
0
1
Compliance Channel
No Equalization
[0:1.5dB] @ 1.25 GHz
[0:2.5dB] @ 1.25 GHz
[0:3.5dB] @ 1.25 GHz
[0:4.5dB] @ 1.25 GHz
[0:5.5dB] @ 1.25 GHz
[0:6.5dB] @ 1.25 GHz
[0:7.5dB] @ 1.25 GHz
3
PS8778E
02/15/06
PI2EQX4402
2.5Gbps x2 Lane Serial PCI Express Repeater / Equalizer
AC/DC Electrical Characteristics for 2.5 Gbps Quad Repeater/Equalizer
(V
DD
= 1.8 ±0.1V)
Symbol
Ps
Parameter
Supply Power
Latency
CML Receiver Input
RL
RX
Return Loss
Differential Input Peak-to-
V
RX-DIFFP-P
peak Voltage
AC Peak Common Mode
V
RX-CM-ACP
Input Voltage
DC Differential Input
Z
RX-DIFF-DC
Impedance
Z
RX-DC
DC Input Impedance
Equalization
J
RS
J
RM
Residual Jitter
(1,2)
Random Jitter
(1,2)
Total Jitter
Deterministic jitter
1.5
0.3
0.2
Ulp-p
psrms
Conditions
EN = LVCMOS Low
EN = LVCMOS High
From input to output
Min.
Typ.
Max.
0.1
0.6
Units
W
ns
2.0
50 MHz to 1.25 GHz
0.175
12
1.200
150
80
40
100
50
120
60
dB
V
mV
Ω
Notes
1. K28.7 pattern is applied differentially at point A as shown in Figure 1.
2. Total jitter does not include the signal source jitter. Total jitter (TJ) = (14.1 × RJ + DJ) where RJ is random RMS jitter and DJ is maximum
deterministic jitter. Signal source is a K28.5 ± pattern (00 1111 1010 11 0000 0101) for the deterministic jitter test and K28.7 (0011111000) or
equivalent for random jitter test. Residual jitter is that which remains after equalizing media-induced losses of the environment of Figure 1 or
its equivalent. The deterministic jitter at point B must be from media-induced loss, and not from clock source modulation. Jitter is measured at
0V at point C of Figure 1.
FR4
Signal
Source
A
B
Pericom
PI2EQX4402
In
Out
C
SmA
Connector
30
IN
SmA
Connector
Figure 1. Test Condition Referenced in the Electrical Characteristic Table
4
PS8778E
02/15/06
PI2EQX4402
2.5Gbps x2 Lane Serial PCI Express Repeater / Equalizer
AC/DC Electrical Characteristics for 2.5 Gbps x2 Lane Repeater/Equalizer
(TA = 0 to 70˚C)
Symbol
Parameter
Conditions
Differential Swing
| V
TX-D+
- V
TX-D-
|
| V
TX-D+
+ V
TX-D-
| / 2
20% to 80%
(1)
Single ended
40
80
75
V
TX-DIFFP-P
= 2 * | V
TX-D+
- V
TX-D-
|
0.8
50
100
Min.
Typ.
Max.
Units
CML Transmitter Output (100Ω differential)
V
DIFFP
V
TX-C
t
F
, t
R
Z
OUT
Z
TX-DIFF-DC
C
TX
V
TX-DIFFP-P
Output Voltage Swing
Common-Mode Voltage
Transition Time
Output resistance
DC Differential TX Impedance
AC Coupling Capacitor
Differential Peak-to-peak Ouput
Voltage
400
V
DD
-
0.3
150
60
120
200
1.8
ps
Ω
Ω
nF
V
900
mVp-p
LVCMOS Control Pins
V
IH
V
IL
I
IH
I
IL
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
0.65 ×
V
DD
V
DD
0.35 ×
V
DD
250
500
V
µA
Note:
1. Using K28.7 (0011111000) pattern)
5
PS8778E
02/15/06
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