74AHC273PW-T datasheet, PDF - EEWORLD Datasheet

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74AHC273PW-T: DescriptionIC AHC SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20, 4.40 MM, PLASTIC, MO-153, SOT-360-1, TSSOP-20, FF/Latch; Categorylogic; File Size95KB，18 Pages; ManufacturerNXP; Websitehttps://www.nxp.com; Environmental Compliance

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74AHC273PW-T Overview

IC AHC SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20, 4.40 MM, PLASTIC, MO-153, SOT-360-1, TSSOP-20, FF/Latch

74AHC273PW-T Parametric

Parameter Name	Attribute value
Source Url Status Check Date	2013-06-14 00:00:00
Is it Rohs certified?	conform to
Maker	NXP
Parts packaging code	TSSOP
package instruction	4.40 MM, PLASTIC, MO-153, SOT-360-1, TSSOP-20
Contacts	20
Reach Compliance Code	unknown
Is Samacsys	N
series	AHC
JESD-30 code	R-PDSO-G20
JESD-609 code	e4
length	6.5 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	D FLIP-FLOP
Maximum Frequency@Nom-Sup	70000000 Hz
MaximumI(ol)	0.008 A
Humidity sensitivity level	1
Number of digits	8
Number of functions	1
Number of terminals	20
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP20,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packing	TAPE AND REEL
Peak Reflow Temperature (Celsius)	260
power supply	2/5.5 V
Prop。Delay @ Nom-Sup	14 ns
propagation delay (tpd)	21.5 ns
Certification status	Not Qualified
Maximum seat height	1.1 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	2 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	NICKEL PALLADIUM GOLD
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
Trigger type	POSITIVE EDGE
width	4.4 mm
minfmax	100 MHz
Base Number Matches	1

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74AHC273; 74AHCT273

Octal D-type ﬂip-ﬂop with reset; positive-edge trigger

Rev. 03 — 13 May 2008

Product data sheet

1. General description

The 74AHC273; 74AHCT273 is a high-speed Si-gate CMOS device and is pin compatible

with Low-power Schottky TTL (LSTTL). It is speciﬁed in compliance with JEDEC standard

No. 7-A.

The 74AHC273; 74AHCT273 has eight edge-triggered, D-type ﬂip-ﬂops with individual D

inputs and Q outputs.

The common clock (CP) and master reset (MR) inputs, load and reset (clear) all ﬂip-ﬂops

simultaneously.

The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is

transferred to the corresponding output (Qn) of the ﬂip-ﬂop.

All outputs will be forced LOW, independent of clock or data inputs, by a LOW on the MR

input.

The device is useful for applications where only the true output is required and the clock

and master reset are common to all storage elements.

2. Features

Balanced propagation delays

All inputs have Schmitt-trigger actions

Inputs accept voltages higher than V

Ideal buffer for MOS microcontroller or memory

Common clock and master reset

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