PCF8593TD datasheet, PDF - EEWORLD Datasheet

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PCF8593TD: DescriptionReal Time Clock LO PWR CLOCK/CAL; CategoryThe embedded processor and controller Microcontrollers and processors; File Size219KB，36 Pages; ManufacturerNXP; Websitehttps://www.nxp.com

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PCF8593TD Overview

Real Time Clock LO PWR CLOCK/CAL

PCF8593TD Parametric

Parameter Name	Attribute value
Maker	NXP
Parts packaging code	SOIC
package instruction	SOP,
Contacts	8
Reach Compliance Code	unknown
ECCN code	EAR99
maximum clock frequency	0.032 MHz
Information access methods	I2C
JESD-30 code	R-PDSO-G8
length	4.9 mm
Number of terminals	8
Number of timers
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Certification status	Not Qualified
Maximum seat height	1.75 mm
Maximum supply voltage	6 V
Minimum supply voltage	2.5 V
Nominal supply voltage	3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
width	3.9 mm
uPs/uCs/peripheral integrated circuit type	TIMER, REAL TIME CLOCK

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PCF8593

Low power clock and calendar

Rev. 04 — 6 October 2010

Product data sheet

1. General description

The PCF8593 is a CMOS

clock and calendar circuit, optimized for low power

consumption. Addresses and data are transferred serially via the two-line bidirectional

C-bus. The built-in word address register is incremented automatically after each written

or read data byte. The built-in 32.768 kHz oscillator circuit and the first 8 bytes of the RAM

are used for the clock, calendar, and counter functions. The next 8 bytes can be

programmed as alarm registers or used as free RAM space.

2. Features and benefits

C-bus interface operating supply voltage: 2.5 V to 6.0 V

Clock operating supply voltage 1.0 V to 6.0 V at 0

°C

to +70

°C

8 bytes scratchpad RAM (when alarm not used)

Data retention voltage: 1.0 V to 6.0 V

External RESET input resets I

C interface only

Operating current (at f

SCL

= 0 Hz, 32 kHz time base, V

= 2.0 V): typical 1

μA

Clock function with four year calendar

Universal timer with alarm and overflow indication

24 hour or 12 hour format

32.768 kHz or 50 Hz time base

Serial input and output bus (I

C-bus)

Automatic word address incrementing

Programmable alarm, timer, and interrupt function

Space-saving SO8 package available

Slave addresses: A3h for reading, A2h for writing

3. Ordering information

Table 1.

Ordering information

Package

Name

PCF8593P

PCF8593T

DIP8

SO8

Description

plastic dual in-line package; 8 leads (300 mil)

plastic small outline package; 8 leads;

body width 3.9 mm

Version

SOT97-1

SOT96-1

Type number

The definition of the abbreviations and acronyms used in this data sheet can be found in

Section 14.

NXP Semiconductors

PCF8593

Low power clock and calendar

7. Functional description

The PCF8593 contains sixteen 8 bit registers with an 8 bit auto-incrementing address

bidirectional I

C-bus interface.

The first 8 registers (memory addresses 00h to 07h) are designed as addressable 8 bit

parallel registers. The first register (memory address 00h) is used as a control and status

The memory addresses 08h to 0Fh may be programmed as alarm registers or used as

free RAM locations.

7.1 Counter function modes

When the control and status register is programmed, a 32.768 kHz clock mode, a 50 Hz

clock mode or an event-counter mode can be selected.

In the clock modes the hundredths of a second, seconds, minutes, hours, date, month

(four year calendar) and weekday are stored in a Binary Coded Decimal (BCD) format.

The timer register stores up to 99 days. The event counter mode is used to count pulses

applied to the oscillator input (OSCO left open-circuit). The event counter stores up to 6

digits of data.

When one of the counters is read (memory locations 01h to 07h), the contents of all

counters are strobed into capture latches at the beginning of a read cycle. Therefore,

faulty reading of the counter during a carry condition is prevented. When a counter is

written, other counters are not affected.

7.2 Alarm function modes

By setting the alarm enable bit of the control and status register the alarm control register

(address 08h) is activated.

By setting the alarm control register, a dated alarm, a daily alarm, a weekday alarm, or a

timer alarm may be programmed. In the clock modes, the timer register (address 07h)

may be programmed to count hundredths of a second, seconds, minutes, hours, or days.

Days are counted when an alarm is not programmed.

Whenever an alarm event occurs the alarm flag of the control and status register is set. A

timer alarm event will set the alarm flag and an overflow condition of the timer will set the

timer flag. The open-drain interrupt output is switched on (active LOW) when the alarm or

timer flag is set (enabled). The flags remain set until directly reset by a write operation.

When the alarm is disabled (bit 2 of control and status register set logic 0) the alarm

registers at addresses 08h to 0Fh may be used as free RAM.

PCF8593

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 04 — 6 October 2010

4 of 35

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