Operating Temperature Range ........................ -40NC to +125NC
Junction Temperature .....................................................+150NC
Storage Temperature Range............................ -65NC to +150NC
Soldering Temperature (reflow) ......................................+260NC
PACKAGE THERMAL CHARACTERISTICS (Note 1)
SO-EP
Junction-to-Ambient Thermal Resistance (q
JA
) ..........41°C/W
Junction-to-Case Thermal Resistance (q
JC
) .................7°C/W
TDFN-EP
Junction-to-Ambient Thermal Resistance (q
JA
) ..........42°C/W
Junction-to-Case Thermal Resistance (q
JC
) .................8°C/W
Note 1:
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-lay-
er board. For detailed information on package thermal considerations, refer to
www.maximintegrated.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
CC
= +15V, V
EE
= -15V, V
CM
= 0V, R
L
= 10kI to V
GND
= 0V, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at
T
A
= +25NC.) (Note 2)
PARAMETER
POWER SUPPLY
Supply Voltage Rang
e
Supply Current
V
CC
- V
EE
I
CC
Guaranteed by PSRR
T
A
= +25NC
Per amplifier
+4.5V
P
(V
CC
- V
EE
)
P
+36V
T
A
= +25NC
-40NC
P
T
A
P
+125NC
-40NC
P
T
A
P
+125NC
(V
EE
+ 0.45V)
P
V
CM
P
(V
CC
- 1.8V)
V
EE
P
V
CM
P
(V
CC
- 1.8V)
(V
EE
+ 0.45V)
P
V
CM
P
(V
CC
- 1.8V)
V
EE
P
V
CM
P
(V
CC
- 1.8V)
T
A
= +25NC
Input Voltage Range
V
IN+
, V
IN-
Guaranteed by CMRR
-40NC
P
T
A
P
+125NC
V
EE
V
EE
106
105
130
130
dB
0.2
Q42
4.5
Q30
Q200
-40NC
P
T
A
P
+85NC
-40NC
P
T
A
P
+125NC
Power-Supply Rejection Ratio
DC SPECIFICATIONS
Input Offset Voltage
Input Offset Voltage Drift
(Note 3)
Input Bias Current
Input Offset Current
V
OS
DV
OS
I
B
I
OS
Q70
Q200
Q290
0.9
Q400
22
Q300
Q2000
V
CC
-
1.7
V
CC
-
1.8
FV
FV/NC
nA
FA
nA
PSRR
T
A
= +25NC
-40NC
P
T
A
P
+125NC
112
110
135
4.5
3.5
36
5
6
6.5
dB
mA
V
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
EE
P
V
CM
P
(V
CC
- 1.7V), T
A
= +25NC
Common-Mode Rejection Ratio
CMRR
V
EE
P
V
CM
P
(V
CC
- 1.8V), -40NC
P
T
A
P
+125NC
2
Maxim Integrated
MAX9633
Dual 36V Op Amp for 18-Bit
SAR ADC Front-End
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +15V, V
EE
= -15V, V
CM
= 0V, R
L
= 10kI to V
GND
= 0V, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at
T
A
= +25NC.) (Note 2)
PARAMETER
Open-Loop Gain
SYMBOL
A
VOL
V
OH
Output Voltage Swing
V
OL
V
OUT
- V
EE
CONDITIONS
(V
EE
+ 0.3V)
P
V
OUT
P
(V
CC
- 2V), R
L
= 10kI
(V
EE
+ 0.45V)
P
V
OUT
P
(V
CC
- 2.1V), R
L
= 1kI
V
CC
- V
OUT
R
L
= 10kI
R
L
= 1kI
R
L
= 10kI
R
L
= 1kI
R
L
= 10kI to V
EE
R
L
= 1kI to V
EE
Short-Circuit Current
AC SPECIFICATIONS
Gain Bandwidth
Slew Rate
Output Transient Recovery Time
GBWP
SR
t
TR
5V step, R
S
= 20I, C
L
= 1nF, A
V
= 1V/V
To 0.001%,
DV
OUT
= 200mV, R
S
= 20I, C
L
= 1nF, AV = +1V/V
To 0.001%, 5V step,
AV = -1V/V
V
OUT
= 10V
P-P
, R
S
=
20I, C
L
= 1nF, A
V
=
+1V/V
V
OUT
= 10V
P-P
, R
S
=
20I, C
L
= 1nF
e
n
f = 100Hz
f = 1kHz
0.1Hz
P
f
P
10Hz
i
n
C
L
f = 100Hz
f = 1kHz
No sustained oscillation, A
V
= +1V/V
R
S
= 100I, C
L
=
30pF
R
S
= 20I, C
L
=
1nF
f = 1kHz
f = 10kHz
f = 100kHz
f = 1kHz
f = 10kHz
27
18
500
750
ns
750
145
130
-100
-100
-90
3.5
3
250
12
10
50
dB
nV/√Hz
nV
P-P
pA/√Hz
pF
dB
MHz
V/Fs
ns
I
SC
T
A
= +25NC
MIN
118
115
TYP
140
138
1.6
1.7
70
170
20
20
50
1.9
2.0
150
300
100
100
mA
mV
MAX
UNITS
dB
V
Settling Time
t
S
Total Harmonic Distortion
THD
Crosstalk
Input Voltage Noise Density
Input Voltage Noise
Input Current Noise Density
Capacitive Loading
Note 2:
All devices are 100% production tested at T
A
= +25NC. Temperature limits are guaranteed by design.
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