MC10E143, MC100E143
5 V ECL 9‐Bit Hold Register
Description
The MC10E/100E143 is a 9-bit holding register, designed with
byte-parity applications in mind. The E143 holds current data or loads
new data, with the nine inputs D0
−
D8 accepting parallel input data.
The SEL (Select) input pin is used to switch between the two modes
of operation
−
HOLD and LOAD. Input data is accepted by the
registers a set-up time before the positive going edge of CLK1 or
CLK2. A HIGH on the Master Reset pin (MR) asynchronously resets
all the registers to zero.
The 100 Series contains temperature compensation.
Features
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•
•
•
•
•
•
•
•
•
•
•
•
•
700 MHz Min. Operating Frequency
9-Bit for Byte-Parity Applications
Asynchronous Master Reset
Dual Clocks
PECL Mode Operating Range:
♦
V
CC
= 4.2 V to 5.7 V with V
EE
= 0 V
NECL Mode Operating Range:
♦
V
CC
= 0 V with V
EE
=
−4.2
V to
−5.7
V
Internal Input 50 kW Pulldown Resistors
ESD Protection:
♦
Human Body Model; > 2 kV
♦
Machine Model; > 200 V
Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level: 3 (Pb-Free)
♦
For Additional Information, see Application Note
AND8003/D
Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
Transistor Count = 484 devices
These Devices are Pb-Free, Halogen Free and are RoHS Compliant
PLCC−28
FN SUFFIX
CASE 776−02
MARKING DIAGRAM*
1
MCxxxE143FNG
AWLYYWW
xxx
A
WL
YY
WW
G
= 10 or 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb-Free Package
*For additional marking information, refer to
Application Note
AND8002/D.
ORDERING INFORMATION
Device
MC10E143FNR2G
MC100E143FNG
Package
PLCC−28
(Pb-Free)
PLCC−28
(Pb-Free)
Shipping
†
500/Tape & Reel
37 Units/Tube
†For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure,
BRD8011/D.
©
Semiconductor Components Industries, LLC, 2016
July, 2016
−
Rev. 8
1
Publication Order Number:
MC10E143/D
MC10E143, MC100E143
SEL
25
MR
CLK1
CLK2
V
EE
NC
D
0
D
1
26
27
28
1
D
8
24
D
7
23
D
6
22
D
5
21
V
CCO
20
Q
8
19
18
17
16
Q
7
Q
6
V
CC
Q
5
V
CCO
Q
4
Q
3
D
3
D
2
MUX
D
1
MUX
D
R
D
R
D
Q
1
D
0
MUX
D
R
Q
0
Q
2
2
3
4
5
D
2
Pinout: 28-Lead PLCC
(Top View)
15
14
13
12
MUX
R
Q
3
6
D
3
7
8
9
10
Q
1
11
Q
2
D
8
SEL
CLK1
CLK2
MR
MUX
D
Q
8
D
4
V
CCO
Q
0
* All V
CC
and V
CCO
pins are tied together on the die.
Warning: All V
CC
, V
CCO
, and V
EE
pins must be externally
connected to Power Supply to guarantee proper operation.
R
Figure 1. 28-Lead Pinout
Figure 2. Logic Diagram
Table 1. PIN DESCRIPTION
PIN
D
0
−
D
8
SEL
CLK1, CLK2
MR
Q
0
−
Q
8
NC
V
CC
, V
CCO
V
EE
FUNCTION
ECL Parallel Data Inputs
ECL Mode Select Input
ECL Clock Inputs
ECL Master Reset
ECL Data Outputs
No Connect
Positive Supply*
Negative Supply
*From V
CC
pin to each V
CCO
pin is an internal 100
W
resistor.
Table 2. FUNCTIONS
SEL
L
H
Load
Hold
Mode
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2
MC10E143, MC100E143
Table 3. MAXIMUM RATINGS
Symbol
V
CC
V
EE
V
I
I
out
T
A
T
stg
q
JA
q
JC
V
EE
T
sol
Parameter
PECL Mode Power Supply
NECL Mode Power Supply
PECL Mode Input Voltage
NECL Mode Input Voltage
Output Current
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction-to-Ambient)
Thermal Resistance (Junction-to-Case)
PECL Operating Range
NECL Operating Range
Wave Solder (Pb-Free)
0 lfpm
500 lfpm
Standard Board
PLCC−28
PLCC−28
Condition 1
V
EE
= 0 V
V
CC
= 0 V
V
EE
= 0 V
V
CC
= 0 V
Continuous
Surge
V
I
≤
V
CC
V
I
≥
V
EE
Condition 2
Rating
8
−8
6
−6
50
100
0 to +85
−65
to +150
63.5
43.5
22 to 26
4.2 to 5.7
−5.7
to
−4.2
265
Unit
V
V
V
mA
°C
°C
°C/W
°C/W
V
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
Table 4. 10E SERIES PECL DC CHARACTERISTICS
(V
CCx
= 5.0 V; V
EE
= 0.0 V (Note 1))
0°C
Symbol
I
EE
V
OH
V
OL
V
IH
V
IL
I
IH
I
IL
Characteristic
Power Supply Current
Output HIGH Voltage (Note 2)
Output LOW Voltage (Note 2)
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
0.5
0.3
3980
3050
3830
3050
Min
Typ
120
4070
3210
3995
3285
Max
145
4160
3370
4160
3520
150
0.5
0.25
4020
3050
3870
3050
Min
25°C
Typ
120
4105
3210
4030
3285
Max
145
4190
3370
4190
3520
150
0.3
0.2
4090
3050
3940
3050
Min
85°C
Typ
120
4185
3227
4110
3302
Max
145
4280
3405
4280
3555
150
Unit
mA
mV
mV
mV
mV
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary
−0.46
V / +0.06 V.
2. Outputs are terminated through a 50
W
resistor to V
CC
−
2.0 V.
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MC10E143, MC100E143
Table 5. 10E SERIES NECL DC CHARACTERISTICS
(V
CCx
= 0.0 V; V
EE
=
−5.0
V (Note 1))
0°C
Symbol
I
EE
V
OH
V
OL
V
IH
V
IL
I
IH
I
IL
Characteristic
Power Supply Current
Output HIGH Voltage (Note 2)
Output LOW Voltage (Note 2)
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
0.5
0.3
−1020
−1950
−1170
−1950
Min
Typ
120
−930
−1790
−1005
−1715
Max
145
−840
−1630
−840
−1480
150
0.5
0.065
−980
−1950
−1130
−1950
Min
25°C
Typ
120
−895
−1790
−970
−1715
Max
145
−810
−1630
−810
−1480
150
0.3
0.2
−910
−1950
−1060
−1950
Min
85°C
Typ
120
−815
−1773
−890
−1698
Max
145
−720
−1595
−720
−1445
150
Unit
mA
mV
mV
mV
mV
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary
−0.46
V / +0.06 V.
2. Outputs are terminated through a 50
W
resistor to V
CC
−
2.0 V.
Table 6. 100E SERIES PECL DC CHARACTERISTICS
(V
CCx
= 5.0 V; V
EE
= 0.0 V (Note 1))
0°C
Symbol
I
EE
V
OH
V
OL
V
IH
V
IL
I
IH
I
IL
Characteristic
Power Supply Current
Output HIGH Voltage (Note 2)
Output LOW Voltage (Note 2)
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
0.5
0.3
3975
3190
3835
3190
Min
Typ
120
4050
3295
3975
3355
Max
145
4120
3380
4120
3525
150
0.5
0.25
3975
3190
3835
3190
Min
25°C
Typ
120
4050
3255
3975
3355
Max
145
4120
3380
4120
3525
150
0.5
0.2
3975
3190
3835
3190
Min
85°C
Typ
138
4050
3260
3975
3355
Max
165
4120
3380
4120
3525
150
Unit
mA
mV
mV
mV
mV
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary
−0.46
V / +0.8 V.
2. Outputs are terminated through a 50
W
resistor to V
CC
−
2.0 V.
Table 7. 100E SERIES NECL DC CHARACTERISTICS
(V
CCx
= 0.0 V; V
EE
=
−5.0
V (Note 1))
0°C
Symbol
I
EE
V
OH
V
OL
V
IH
V
IL
I
IH
I
IL
Characteristic
Power Supply Current
Output HIGH Voltage (Note 2)
Output LOW Voltage (Note 2)
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
0.5
0.3
−1025
−1810
−1165
−1810
Min
Typ
120
−950
−1705
−1025
−1645
Max
145
−880
−1620
−880
−1475
150
0.5
0.25
−1025
−1810
−1165
−1810
Min
25°C
Typ
120
−950
−1745
−1025
−1645
Max
145
−880
−1620
−880
−1475
150
0.5
0.2
−1025
−1810
−1165
−1810
Min
85°C
Typ
138
−950
−1740
−1025
−1645
Max
165
−880
−1620
−880
−1475
150
Unit
mA
mV
mV
mV
mV
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary
−0.46
V / +0.8 V.
2. Outputs are terminated through a 50
W
resistor to V
CC
−
2.0 V.
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MC10E143, MC100E143
Table 8. AC CHARACTERISTICS
(V
CCx
= 5.0 V; V
EE
= 0.0 V or V
CCx
= 0.0 V; V
EE
=
−5.0
V (Note 1)
)
0°C
Symbol
f
SHIFT
t
PLH
t
PHL
25°C
Max
Min
700
1000
1000
600
600
50
300
300
75
900
400
Typ
900
800
800
−100
150
100
−150
700
1000
1000
Max
Min
700
600
600
50
300
300
75
900
400
75
<1
800
300
525
800
300
85°C
Typ
900
800
800
−100
150
100
−150
700
1000
1000
Max
Unit
MHz
ps
Characteristic
Max. Shift Frequency
Propagation Delay To Output
Clk
MR
Setup Time
D
SEL
Hold Time
D
SEL
Reset Recovery Time
Minimum Pulse Width
Clk, MR
Within-Device Skew (Note 2)
Random Clock Jitter (RMS)
Rise/Fall Times
(20 - 80%)
Min
700
600
600
50
300
300
75
900
400
Typ
900
800
800
−100
150
100
−150
700
t
s
ps
t
h
ps
t
RR
t
PW
t
SKEW
t
JITTER
T
r
t
f
ps
ps
75
<1
300
525
75
<1
525
800
ps
ps
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. 10 Series: V
EE
can vary
−0.46
V / +0.06 V.
100 Series: V
EE
can vary
−0.46
V / +0.8 V.
2. Within-device skew is defined as identical transitions on similar paths through a device.
Q
Driver
Device
Q
Z
o
= 50
W
50
W
50
W
D
Z
o
= 50
W
D
Receiver
Device
V
TT
V
TT
= V
CC
−
2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note
AND8020/D
−
Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
−
ECL Clock Distribution Techniques
−
Designing with PECL (ECL at +5.0 V)
−
ECLinPSt I/O SPiCE Modeling Kit
−
Metastability and the ECLinPS Family
−
Interfacing Between LVDS and ECL
−
The ECL Translator Guide
−
Odd Number Counters Design
−
Marking and Date Codes
−
Termination of ECL Logic Devices
−
Interfacing with ECLinPS
−
AC Characteristics of ECL Devices
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