Pins Description of KSZ8842-PMQL.............................................................................................................................. 11
Functional Overview: PCI Bus Interface Unit............................................................................................................... 20
PCI Bus Interface.......................................................................................................................................................... 20
TXDMA Logic and TX Buffer Manager ......................................................................................................................... 20
RXDMA Logic and RX Buffer Manager ........................................................................................................................ 20
Power Management...................................................................................................................................................... 21
MDI/MDI-X Auto Crossover .......................................................................................................................................... 21
Auto Negotiation ........................................................................................................................................................... 23
Functional Overview: MAC and Switch......................................................................................................................... 25
MAC Operation ............................................................................................................................................................. 28
Inter Packet Gap (IPG) ................................................................................................................................................. 28
Late Collision ................................................................................................................................................................ 28
Spanning Tree Support................................................................................................................................................. 29
IGMP Support ............................................................................................................................................................... 30
Port Mirroring Support................................................................................................................................................... 30
IEEE 802.1Q VLAN Support ......................................................................................................................................... 31
QoS Priority Support ..................................................................................................................................................... 31
DiffServ based Priority .................................................................................................................................................. 32
Rate Limiting Support ................................................................................................................................................... 32
MAC Filtering Function ................................................................................................................................................. 33
Loop back Support........................................................................................................................................................ 33
Host Communication ...................................................................................................................................................... 35
Host Communication Descriptor Lists and Data Buffers .............................................................................................. 35
PCI Control & Status Registers ..................................................................................................................................... 43
MAC DMA Transmit Control Register (MDTXC Offset 0x0000) ................................................................................... 43
MAC DMA Receive Control Register (MDRXC Offset 0x0004).................................................................................... 44
Interrupt Status Register (INTST Offset 0x002C) ......................................................................................................... 48
MAC Additional Station Address Low Register (MAAL0-15) ........................................................................................ 49
MAC Additional Station Address High Register (MAAH0-15)....................................................................................... 49
MAC/PHY and Control Registers ................................................................................................................................... 50
MAC Address Register Low (0x0200): MARL .............................................................................................................. 50
MAC Address Register Middle (0x0202): MARM ......................................................................................................... 50
MAC Address Register High (0x0204): MARH ............................................................................................................. 50
Switch ID and Enable Register (Offset 0x0400): SIDER .............................................................................................. 52
Switch Global Control Register 1 (Offset 0x0402): SGCR1 ......................................................................................... 53
Switch Global Control Register 2 (Offset 0x0404): SGCR2 ......................................................................................... 54
Switch Global Control Register 3 (Offset 0x0406): SGCR3 ......................................................................................... 55
Switch Global Control Register 4 (Offset 0x0408): SGCR4 ......................................................................................... 56
Switch Global Control Register 5 (Offset 0x040A): SGCR5 ......................................................................................... 56
Switch Global Control Register 6 (Offset 0x0410): SGCR6 ......................................................................................... 57
Switch Global Control Register 7 (0x0412): SGCR7 .................................................................................................... 58
Priority Control Register 1 (Offset 0x0480): TOSR1..................................................................................................... 59
TOS Priority Control Register 2 (Offset 0x482): TOSR2 .............................................................................................. 59
TOS Priority Control Register 3 (Offset 0x484): TOSR3 .............................................................................................. 60
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