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LU3X34FTR: DescriptionQuad 3 V 10/100 Ethernet Transceiver TX/FX; File Size368KB，52 Pages; ManufacturerAgere System(LSI Logic)

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LU3X34FTR Overview

Quad 3 V 10/100 Ethernet Transceiver TX/FX

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Preliminary Data Sheet

July 2000

LU3X34FTR

Quad 3 V 10/100 Ethernet Transceiver TX/FX

Overview

The LU3X34FTR is a fully integrated, 4-port

10/100 Mbits/s physical layer device with an inte-

grated transceiver. This part was designed specifi-

cally for 10/100 Mbits/s switches. These applications

typically require stringent functionality in addition to

very tight board space, power, and cost require-

ments. The LU3X34FTR supports RMII and SMII

interfaces, offering the designer multiple reduced pin

count interfaces to save both real estate and cost in

system design. The LU3X34FTR was designed from

the beginning to conform fully with all pertinent spec-

ifications, from the

ISO

IEC

11801 and

EIA

/TIA

568 cabling guidelines to

ANSI

X3.263TP-PMD to

IEEE

802.3 Ethernet specifications.

FX mode configurable on a per-port basis.

Built-in analog 10 Mbit receive filter, removing the

need for external filters.

Built-in 10 bit transmit filter.

10 Mbit PLL, exceeding tolerances for both

preamble and data jitter.

100 Mbit PLL, combined with the digital adaptive

equalizer, robustly handles variations in rise-fall

time, excessive attenuation due to channel loss,

duty-cycle distortion, crosstalk, and baseline

wander.

Transmit rise-fall time manipulated to provide lower

emissions, amplitude fully compatible for proper

interoperability.

Programmable scrambler seed for better FCC

compliancy.

Features

4-port, single-chip, integrated physical layer and

transceivers for 10Base-T, 100Base-TX, or

100Base-FX functions.

IEEE

802.3u Clause 28 compliant autonegotiation

for full 10 Mbits/s and 100 Mbits/s control.

Extended management support with interrupt

capabilities.

PHY MIB support.

Low-power 500 mA max.

— Low-cost 128-pin SQFP packaging with heat

spreader.

IEEE

802.3 compatible 10Base-T and 100Base-T

physical layer interface and ANSI X3.263 TP-PMD

compatible transceiver.

Interface support for RMII and SMII switch

applications.

Autonegotiation pin configurability on a per-port

basis.

ISO

is a registered trademark of The International Organization

of Standardization.

IEC

is a registered trademark of The International Electrotechni-

cal Commission.

EIA

is a registered trademark of Electronic Industries Associa-

tion.

ANSI

is a registered trademark of American National Standards

Institute, Inc.

IEEE

is a registered trademark of The Institute of Electrical and

Electronics Engineers, Inc.

LU3X34FTR

Quad 3 V 10/100 Ethernet Transceiver TX/FX

Preliminary Data Sheet

July 2000

Table of Contents

Contents

Page

Overview................................................................................................................................................................... 1

Features ................................................................................................................................................................... 1

Description................................................................................................................................................................ 4

Pin Information ......................................................................................................................................................... 5

Pin Descriptions........................................................................................................................................................ 7

Functional Description ............................................................................................................................................ 13

Reduced Media Independent Interface (RMII) .................................................................................................... 13

Serial Media Independent Interface (SMII).......................................................................................................... 15

Media Independent Interface (MII)—Internal....................................................................................................... 17

100Base-X Module.............................................................................................................................................. 19

Scrambler Block .................................................................................................................................................. 22

100Base-TX Transceiver..................................................................................................................................... 24

10Base-T Module ................................................................................................................................................ 25

Reset Operation .................................................................................................................................................. 28

MII Registers .......................................................................................................................................................... 30

dc and ac Specifications......................................................................................................................................... 43

Absolute Maximum Ratings................................................................................................................................. 43

Clock Timing........................................................................................................................................................... 44

Outline Diagram...................................................................................................................................................... 50

128-Pin SQFP ..................................................................................................................................................... 50

Ordering Information............................................................................................................................................... 51

Tables

Page

Table 1. MII Interface Cross-Reference ................................................................................................................... 7

Table 2. Twisted-Pair Magnetic Interface ................................................................................................................. 8

Table 3. Twisted-Pair Transceiver Control/Transmitter Control ................................................................................. 8

Table 4. MII Interface (RMII Mode) .......................................................................................................................... 8

Table 5. MII Interface (SMII Mode) .......................................................................................................................... 9

Table 6. LED/Configuration Pins............................................................................................................................ 10

Table 7. Special Mode Configurations ................................................................................................................... 11

Table 8. Clock and Chip Reset .............................................................................................................................. 12

Table 9. Power and Ground ................................................................................................................................... 12

Table 10. Receive Data/Status Encoding .............................................................................................................. 16

Table 11. Symbol Code Scrambler ........................................................................................................................ 21

Table 12. Autonegotiation ...................................................................................................................................... 29

Table 13. MII Management Registers .................................................................................................................... 30

Table 14. Control Register (Register 0h) ............................................................................................................... 30

Table 15. Status Register Bit Definitions (Register 1h).......................................................................................... 32

Table 16. PHY Identifier (Register 2h) ................................................................................................................... 34

Table 17. PHY Identifier (Register 3h) ................................................................................................................... 34

Table 18. Advertisement (Register 4h) .................................................................................................................. 35

Table 19. Autonegotiation Link Partner Ability (Register 5h) ................................................................................. 36

Table 20. Autonegotiation Expansion Register (Register 6h) ................................................................................ 36

Table 21. Programable LED (Register 11h) ........................................................................................................... 37

Table 22. False Carrier Counter (Register 13h) ..................................................................................................... 38

Table 23. Receive Error Counter (Register 15h).................................................................................................... 38

Table 24. PHY Control/Status Register (Register 17h).......................................................................................... 38

Table 25. Config 100 Register (Register 18h)........................................................................................................ 39

Table 26. PHY Address Register (Register 19h) ................................................................................................... 40

Lucent Technologies Inc.

Preliminary Data Sheet

July 2000

LU3X34FTR

Quad 3 V 10/100 Ethernet Transceiver TX/FX

Table of Contents

(continued)

Tables

Page

Table 27. Config 10 Register (Register 1Ah) ..........................................................................................................41

Table 28. Status 100 Register (Register 1Bh) ........................................................................................................41

Table 29. Status 10 Register (Register 1Ch) ..........................................................................................................41

Table 30. Interrupt Mask Register (Register 1Dh) ..................................................................................................42

Table 31. Interrupt Status Register (Register 1Eh).................................................................................................42

Table 32. Absolute Maximum Ratings ....................................................................................................................43

Table 33. Operating Conditions ..............................................................................................................................43

Table 34. dc Characteristics ...................................................................................................................................43

Table 35. Management Clock .................................................................................................................................44

Table 36. RMII Receive Timing...............................................................................................................................45

Table 37. RMII Transmit Timing ..............................................................................................................................45

Table 38. Transmit Timing.......................................................................................................................................46

Table 39. Receive Timing .......................................................................................................................................46

Table 40. SMII Timing.............................................................................................................................................47

Table 41. Reset and Configuration Timing .............................................................................................................48

Table 42. PMD Characteristics ...............................................................................................................................48

Figures

Page

Figure 1. LU3X34FTR Block Diagram......................................................................................................................4

Figure 2. Pin Diagram (RMII Mode) .........................................................................................................................5

Figure 3. Pin Diagram (SMII Mode)..........................................................................................................................6

Figure 4. Functional Description ............................................................................................................................13

Figure 5. RMII Receive Timing from Internal MII Signals.......................................................................................14

Figure 6. SMII Connection Diagram .......................................................................................................................15

Figure 7. Receive Sequence Diagram ...................................................................................................................15

Figure 8. Transmit Sequence Diagram ...................................................................................................................16

Figure 9. 100Base-X Data Path .............................................................................................................................19

Figure 10. 10Base-T Module Data Path.................................................................................................................25

Figure 11. LED Configuration.................................................................................................................................28

Figure 12. Management Clock ...............................................................................................................................44

Figure 13. RMII Receive Timing.............................................................................................................................45

Figure 14. RMII Transmit Timing ............................................................................................................................45

Figure 15. Transmit Timing.....................................................................................................................................46

Figure 16. Receive Timing .....................................................................................................................................46

Figure 17. SMII Timing ...........................................................................................................................................47

Figure 18. Reset and Configuration Timing ...........................................................................................................48

Figure 19. PMD Characteristics .............................................................................................................................48

Figure 20. Connection Diagrams (Single-Channel 10/100BTX Operation)............................................................49

Lucent Technologies Inc.

LU3X34FTR Related Products

	LU3X34FTR	LU3X34FTR-HS128-DB
Description	Quad 3 V 10/100 Ethernet Transceiver TX/FX	Quad 3 V 10/100 Ethernet Transceiver TX/FX

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