BLC8G20LS-400AV
Power LDMOS transistor
Rev. 4 — 24 November 2017
Product data sheet
1. Product profile
1.1 General description
400 W LDMOS packaged asymmetric Doherty power transistor for base station
applications at frequencies from 1800 MHz to 2000 MHz.
Table 1.
Typical performance
Typical RF performance at T
case
= 25
C in an asymmetrical Doherty production test circuit.
V
DS
= 32 V; I
Dq
= 800 mA (main); V
GS(amp)peak
= 0.4 V, unless otherwise specified.
Test signal
1-carrier W-CDMA
f
(MHz)
1805 to 1880
1930 to 1990
[1]
V
DS
(V)
32
32
P
L(AV)
(W)
85
85
G
p
(dB)
15.5
15.5
D
(%)
44
44
ACPR
(dBc)
31
[1]
35
[1]
Test signal: 1-carrier W-CDMA; 3GPP test model 1; 64 DPCH; PAR = 9.6 dB at 0.01% probability on CCDF.
1.2 Features and benefits
Excellent ruggedness
Excellent electrical stability
Suitable for conventional and inverted Doherty
High efficiency
Low thermal resistance providing excellent thermal stability
Lower output capacitance for improved performance in Doherty applications
Designed for low memory effects providing excellent digital pre-distortion capability
Internally matched for ease of use
Integrated ESD protection
Compliant to Directive 2002/95/EC, regarding Restriction of Hazardous Substances
(RoHS)
1.3 Applications
RF power amplifiers for base stations and multi carrier applications in the 1800 MHz to
2000 MHz frequency range
BLC8G20LS-400AV
Power LDMOS transistor
2. Pinning information
Table 2.
Pin
1
2
3
4
5
6
7
[1]
Pinning
Description
drain2 (peak)
drain1 (main)
gate1 (main)
gate2 (peak)
source
video decoupling (peak)
video decoupling (main)
1, 6
aaa-014884
Simplified outline
7
2
1
6
5
Graphic symbol
2, 7
3
3
[1]
4
5
4
Connected to flange.
3. Ordering information
Table 3.
Ordering information
Package
Name Description
BLC8G20LS-400AV
-
Air cavity plastic earless flanged package; 6 leads
Version
SOT1258-1
Type number
4. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DS
V
GS(amp)main
V
GS(amp)peak
T
stg
T
j
[1]
Parameter
drain-source voltage
main amplifier gate-source voltage
peak amplifier gate-source voltage
storage temperature
junction temperature
Conditions
Min
-
0.5
0.5
65
[1]
Max
65
+13
+13
+150
225
Unit
V
V
V
C
C
-
Continuous use at maximum temperature will affect the reliability, for details refer to the online MTF
calculator.
5. Recommended operating conditions
Table 5.
Symbol
T
case
Operating conditions
Parameter
case temperature
Conditions
Min
40
Max
+125
Unit
C
BLC8G20LS-400AV
All information provided in this document is subject to legal disclaimers.
© Ampleon Netherlands B.V. 2017. All rights reserved.
Product data sheet
Rev. 4 — 24 November 2017
2 of 16
BLC8G20LS-400AV
Power LDMOS transistor
6. Thermal characteristics
Table 6.
R
th(j-c)
Thermal characteristics
Conditions
V
DS
= 32 V; I
Dq
= 800 mA (main);
V
GS(amp)peak
= 0.4 V; T
case
= 80
C.
P
L
= 85 W
P
L
= 110 W
0.32
0.31
K/W
K/W
Typ
Unit
thermal resistance from junction
to case
Symbol Parameter
7. Characteristics
Table 7.
DC characteristics
T
j
= 25
C unless otherwise specified.
Symbol
V
(BR)DSS
V
GS(th)
V
GSq
I
DSS
I
DSX
I
GSS
g
fs
R
DS(on)
V
(BR)DSS
V
GS(th)
V
GSq
I
DSS
I
DSX
I
GSS
g
fs
R
DS(on)
Parameter
drain-source breakdown voltage
gate-source threshold voltage
gate-source quiescent voltage
drain leakage current
drain cut-off current
gate leakage current
forward transconductance
drain-source on-state resistance
drain-source breakdown voltage
gate-source threshold voltage
gate-source quiescent voltage
drain leakage current
drain cut-off current
gate leakage current
forward transconductance
drain-source on-state resistance
Conditions
V
GS
= 0 V; I
D
= 1.8 mA
V
DS
= 10 V; I
D
= 180 mA
V
DS
= 32 V; I
D
= 800 mA
V
GS
= 0 V; V
DS
= 28 V
V
GS
= V
GS(th)
+ 3.75 V; V
DS
= 10 V
V
GS
= 11 V; V
DS
= 0 V
V
DS
= 10 V; I
D
= 9.0 A
V
GS
= V
GS(th)
+ 3.75 V; I
D
= 6.3 A
V
GS
= 0 V; I
D
= 3.0 mA
V
DS
= 10 V; I
D
= 300 mA
V
DS
= 32 V; I
D
= 1800 mA
V
GS
= 0 V; V
DS
= 28 V
V
GS
= V
GS(th)
+ 3.75 V; V
DS
= 10 V
V
GS
= 11 V; V
DS
= 0 V
V
DS
= 10 V; I
D
= 15.0 A
V
GS
= V
GS(th)
+ 3.75 V; I
D
= 10.5 A
Min
65
1.5
1.7
-
-
-
-
-
65
1.5
1.7
-
-
-
-
-
Typ
-
1.9
2.1
-
34
-
13
85
-
1.9
2.1
-
50
-
19
55
Max
-
2.3
2.5
2.8
-
280
-
135
-
2.3
2.5
2.8
-
280
-
85
Unit
V
V
V
A
A
nA
S
m
V
V
V
A
A
nA
S
m
Main device
Peak device
Table 8.
RF characteristics
Test signal: 1-carrier W-CDMA; PAR = 9.6 dB at 0.01 % probability on the CCDF; 3GPP test model 1; 1 to 64 DPCH;
f
1
= 1807.5 MHz; f
2
= 1877.5 MHz; RF performance at V
DS
= 32 V; I
Dq
= 800 mA (main); V
GS(amp)peak
= 0.4 V; T
case
= 25
C;
unless otherwise specified; in an asymmetrical Doherty production test circuit in 1805 MHz to 1880 MHz frequency range.
Symbol
G
p
RL
in
D
ACPR
PAR
O
P
L(M)
BLC8G20LS-400AV
Parameter
power gain
input return loss
drain efficiency
adjacent channel power ratio
output peak-to-average ratio
peak output power
Conditions
P
L(AV)
= 85 W
P
L(AV)
= 85 W
P
L(AV)
= 85 W
P
L(AV)
= 85 W
P
L(AV)
= 100 W
P
L(AV)
= 100 W
All information provided in this document is subject to legal disclaimers.
Min
14.5
-
40
-
6.0
400
Typ
15.5
11
44
31
6.7
475
Max
-
7
-
27
-
-
Unit
dB
dB
%
dBc
dB
W
© Ampleon Netherlands B.V. 2017. All rights reserved.
Product data sheet
Rev. 4 — 24 November 2017
3 of 16
BLC8G20LS-400AV
Power LDMOS transistor
8. Test information
8.1 Ruggedness in Doherty operation
The BLC8G20LS-400AV is capable of withstanding a load mismatch corresponding to
VSWR = 10 : 1 through all phases under the following conditions:
•
V
DS
= 28 V; I
Dq
= 800 mA; V
GS(amp)peak
= 0.4 V; f = 1807.5 MHz:
1-carrier W-CDMA; P
L
= 141 W (5 dB OBO); 100 % clipping
•
V
DS
= 32 V; I
Dq
= 800 mA; V
GS(amp)peak
= 0.4 V; f = 1807.5 MHz:
1-carrier W-CDMA; P
L
= 141 W (5 dB OBO); 100 % clipping
8.2 Impedance information
Table 9.
Typical impedance of main device
Measured load-pull data of main device; I
Dq
= 800 mA (main); V
DS
= 32 V; pulsed CW (t
p
= 100
s;
= 10 %).
f
(MHz)
1805
1840
1880
1805
1840
1880
[1]
[2]
Z
S
[1]
()
1.2
j5.2
1.2
j5.3
1.6
j5.9
1.2
j5.2
1.2
j5.3
1.6
j5.9
Z
L
[1]
()
1.3
j4.4
1.2
j4.5
1.2
j4.4
2.5
j4.0
2.5
j4.1
2.6
j3.9
P
L
[2]
(W)
252
249
245
178
182
176
D
[2]
(%)
55.9
55.6
53.1
61.4
61.4
60.8
G
p
[2]
(dB)
18.0
18.1
17.9
20.0
20.2
20.5
Maximum power load
Maximum drain efficiency load
Z
S
and Z
L
defined in
Figure 1.
At 3 dB gain compression.
Table 10. Typical impedance of peak device
Measured load-pull data of peak device; I
Dq
= 1750 mA (peak); V
DS
= 32 V; pulsed CW (t
p
= 100
s;
= 10 %).
f
(MHz)
1805
1840
1880
1805
1840
1880
[1]
[2]
Z
S
[1]
()
1.2
j5.0
1.5
j5.3
2.0
j5.9
1.2
j5.0
1.5
j5.3
2.0
j5.9
Z
L
[1]
()
2.1
j5.4
2.5
j5.3
2.3
j5.5
2.5
j3.8
2.7
j3.7
2.4
j3.8
P
L
[2]
(W)
394
383
378
289
289
284
D
[2]
(%)
50.8
53.5
52.1
57.8
59.4
60.4
G
p
[2]
(dB)
19.0
19.5
19.4
21.4
21.4
21.7
Maximum power load
Maximum drain efficiency load
Z
S
and Z
L
defined in
Figure 1.
At 3 dB gain compression.
BLC8G20LS-400AV
All information provided in this document is subject to legal disclaimers.
© Ampleon Netherlands B.V. 2017. All rights reserved.
Product data sheet
Rev. 4 — 24 November 2017
4 of 16
BLC8G20LS-400AV
Power LDMOS transistor
drain
Z
L
gate
Z
S
001aaf059
Fig 1.
Definition of transistor impedance
8.3 Recommended impedances for Doherty design
Table 11. Typical impedance of main at 1 : 1 load
Measured load-pull data of main device; I
Dq
= 800 mA (main); V
DS
= 32 V; pulsed CW (t
p
= 100
s;
= 10 %).
f
(MHz)
1805
1840
1880
[1]
[2]
Z
S
[1]
()
1.0
j4.8
1.1
j5.0
1.4
j5.2
Z
L
[1]
()
1.8
j4.9
1.7
j4.6
1.7
j4.3
P
L(3dB)
[2]
(W)
179
189
183
D
[2]
(%)
50.4
51.6
49.3
G
p
[2]
(dB)
18.1
18.3
18.5
Z
S
and Z
L
defined in
Figure 1.
At P
L(AV)
= 85 W.
Table 12. Typical impedance of main device at 1 : 2.5 load
Measured load-pull data of main device; I
Dq
= 800 mA (main); V
DS
= 32 V; pulsed CW (t
p
= 100
s;
= 10 %).
f
(MHz)
1805
1840
1880
[1]
[2]
Z
S
[1]
()
1.0
j4.8
1.1
j5.0
1.4
j5.2
Z
L
[1]
()
3.1
j3.5
3.3
j4.0
3.3
j4.2
P
L(3dB)
[2]
(W)
132
126
126
D
[2]
(%)
51.1
50.5
50.7
G
p
[2]
(dB)
19.7
19.9
19.9
Z
S
and Z
L
defined in
Figure 1.
At P
L(AV)
= 85 W.
Table 13. Typical impedance of peak device at 1 : 1 load
Measured load-pull data of peak device; I
Dq
= 1750 mA (peak); V
DS
= 32 V; pulsed CW (t
p
= 100
s;
= 10 %).
f
(MHz)
1805
1840
1880
[1]
[2]
Z
S
[1]
()
1.2
j5.0
1.5
j5.3
2.0
j5.9
Z
L
[1]
()
2.8
j4.8
2.7
j4.6
2.6 j4.3
P
L(3dB)
[2]
(W)
316
313
290
D
[2]
(%)
50.0
51.4
52.9
G
p
[2]
(dB)
19.0
19.4
20.0
Z
S
and Z
L
defined in
Figure 1.
At P
L(AV)
= 85 W.
BLC8G20LS-400AV
All information provided in this document is subject to legal disclaimers.
© Ampleon Netherlands B.V. 2017. All rights reserved.
Product data sheet
Rev. 4 — 24 November 2017
5 of 16
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