ZL38005GGG2 datasheet, PDF - EEWORLD Datasheet

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ZL38005GGG2: DescriptionCommunication ICs - Various Pb Free Galileo Voice Processor; CategoryWireless rf/communication Telecom circuit; File Size680KB，11 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com; Environmental Compliance

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Communication ICs - Various Pb Free Galileo Voice Processor

ZL38005GGG2 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Microsemi
Objectid	1846164701
Parts packaging code	BGA
package instruction	TFBGA,
Contacts	96
Reach Compliance Code	compliant
compound_id	6913627
filter	YES
JESD-30 code	S-PBGA-B96
JESD-609 code	e3
length	7 mm
Number of functions	1
Number of terminals	96
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Package shape	SQUARE
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Certification status	Not Qualified
Maximum seat height	1.01 mm
Nominal supply voltage	1.2 V
surface mount	YES
Telecom integrated circuit types	ADPCM CODEC
Temperature level	INDUSTRIAL
Terminal surface	MATTE TIN
Terminal form	BALL
Terminal pitch	0.5 mm
Terminal location	BOTTOM
width	7 mm

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ZL38005

Enhanced Voice Processor

with Dual Wideband Codecs

Data Sheet

A full Design Manual is available to qualified

customers. To register, please send an email to

VoiceProcessing@Zarlink.com.

November 2012

Ordering Information

ZL38005QCG1

ZL38005GGG2

100 Pin LQFP*

96 Pin VFBGA*

*Pb Free Matte Tin

-40C to +85C

Trays, Bake &

Drypack

Trays, Bake &

Drypack

Features

•

100 MHz (200 MIPs) Microsemi voice processor

with hardware accelerator.

Dual narrow band (8 KHz)



ADCs with input

buffer gain selection

Dual narrow band (8 KHz)

DACs

Dual function Inter-IC Sound (I

S) port

PCM port supports TDM (ST BUS, GCI or McBSP

framing) or SSI modes at bit rates of 128, 256, 512,

1024, 2048, 4096, 8192 or 16384 Kb/sec

Separate slave (microcontroller) and master

(Flash) SPI ports, maximum clock rate = 25 MHz

11 General Purpose Input/Output (GPIO) pins

General purpose UART port

Bootloadable for future Microsemi software

upgrades

Buffer

CODEC[0]

ADC

DAC

Driver

Buffer

CODEC[1]

ADC

DAC

Driver

PCM P0

IRQ

•

External oscillator or crystal/ceramic resonator

1.2 V Core; 3.3 V IO with 5 V-tolerant inputs

IEEE-1149.1 compatible JTAG port

Applications

•

Hands-free car kits

Full duplex speaker-phone for digital telephone

Echo cancellation for video conferences

Intercom Systems

Security Systems

•

APLL

Interrupt

Controller

Instruction

Memory

ROM

DSP

Core

PCM P0

Clock

OSCo

OSC

OSCi

PCM_CLKi

PCM_LBCi

JTAG

RAM

Timing

Generator

Master

SPI

Slave

SPI

UART

GPIO

Hardware

Accelerator

Data RAM

Figure 1 - Functional Block Diagram

ZL38005

2.0

Core DSP Functional Block

Data Sheet

The ZL38005 DSP Core functional block, illustrated in Figure 1, is made up of a DSP Core, Interrupt Controller,

Data RAM, Instruction RAM, BOOT ROM Hardware Accelerators. This block controls the timing (APLL and Timing

Generator), peripheral interfaces through a peripheral address/data/control bus.

The ZL38005 implementation of DSP core and Filter Co-processor have been optimized to efficiently support voice

processing applications. These applications are described in detail in the Firmware Manuals associated with this

hardware platform.

2.1

DSP

The Core DSP is a 100 MIPS processor realized with two internal memory busses (Harvard architecture) to allow

multiple accesses during the same instruction cycle. In addition the DSP uses hardware accelerators and a filter co

processor that can be reused for different applications.

The Filter Co-Processor is used by the application firmware to realize the LMS filters up to a maximum of 2048

coefficients (taps).

3.0

Codec[1:0]

The ZL38005 has two 16-bit fully differential



DACs (DAC 0/1) that meets G.712 requirements at 8 kHz sampling

The ADC path consists of input signal pins C0/1_ADCi+ and C0/1_ADCi- (buffer output pins C0/1_BF0+ and

C0/1_BFo-), which feed selectable Microphone Amplifier or Line Amplifier options. The ADC sampling is 8KHz.

4.0

4.1

PCM Port

The PCM port support data communication between an external peripheral device and the ZL38005 DSP Core

using separate input (PCMi) and output (PCMo) serial streams with TDM (i.e., ST-BUS, GCI or McBSP) or SSI

interface timing. Access to the control and status registers associated with these ports is through the Slave SPI port

UART. These port signals are either in their input or high impedance states after a power-on reset and outputs

signals PCMo may be put in a high impedance state at any time during normal operation. Refer to the associated

Firmware Manual for PCM port control, status and mode selection.

Figure 2 illustrates the signals associated with the Master and Slave timing modes of operation for PCM Port. Insert

A: PCM port Master TDM (Mode 0), shows data clock (PCM_CLKo) and frame pulse (PCMFP) as outputs derived

from the ZL38005 internal PLL. PCM_CLKo clocks data into the ZL38005 on PCMCMi and out of the ZL38005 on

PCMo, and PCMFP delineates the 8 kHz frame boundaries for these signals. Insert B: PCM Master SSI (Mode3),

functions the same way as the TDM Master except that selected channels are defined by enable outputs P0ENA1

and P0ENA2.

With slave operation the source of timing is not the ZL38005, so PCM_CLKi is the input clock and PCMFP is the

8 kHz input frame pulse. This is illustrated by Figure 2 C: PCM Port Slave TDM (Modes 1 & 2) and D: PCM Port

Slave SSI (Modes 4, 5 & 6).

Microsemi Corporation

ZL38005GGG2 Related Products

	ZL38005GGG2	ZL38005QCG1
Description	Communication ICs - Various Pb Free Galileo Voice Processor	Communication ICs - Various Pb Free Galileo Voice Processor
Is it Rohs certified?	conform to	conform to
Maker	Microsemi	Microsemi
Parts packaging code	BGA	QFP
package instruction	TFBGA,	LFQFP,
Contacts	96	100
Reach Compliance Code	compliant	compliant
filter	YES	YES
JESD-30 code	S-PBGA-B96	S-PQFP-G100
JESD-609 code	e3	e3
length	7 mm	14 mm
Number of functions	1	1
Number of terminals	96	100
Operating mode	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TFBGA	LFQFP
Package shape	SQUARE	SQUARE
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH
Certification status	Not Qualified	Not Qualified
Maximum seat height	1.01 mm	1.6 mm
Nominal supply voltage	1.2 V	1.2 V
surface mount	YES	YES
Telecom integrated circuit types	ADPCM CODEC	ADPCM CODEC
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal surface	MATTE TIN	MATTE TIN
Terminal form	BALL	GULL WING
Terminal pitch	0.5 mm	0.5 mm
Terminal location	BOTTOM	QUAD
width	7 mm	14 mm

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