STE100P
10/100 FAST ETHERNET 3.3V TRANSCEIVER
1
DESCRIPTION
Figure 1. Package
The STE100P, also referred to as STEPHY1, is a
high performance Fast Ethernet physical layer in-
terface for 10Base-T and 100Base-TX applica-
tions.
It was designed with advanced CMOS technology
to provide a Media Independent Interface (MII) for
easy attachment to 10/100 Media Access Control-
lers (MAC) and a physical media interface for
100Base-TX of IEEE802.3u and 10Base-T of
IEEE802.3.
The STEPHY1 supports both half-duplex and full-
duplex operation, at 10 and 100 Mbps operation.
Its operating mode can be set using auto-negotia-
tion, parallel detection or manual control. It also al-
lows for the support of auto-negotiation functions
for speed and duplex detection.
TQFP64 (10x10x1.40mm)
Table 1. Order Codes
Part Number
STE100P
E-STE100P
(*)
(*) ECOPACK® (see
Section 9)
Package
TQFP64
TQFP64
■
■
2
FEATURES
■
■
2.1 Industry standard
■
IEEE802.3u 100Base-TX and IEEE802.3
10Base-T compliant
Figure 2. Block Diagram
LEDS
■
Support for IEEE802.3x flow control
IEEE802.3u Auto-Negotiation support for
10Base-T and 100Base-TX
MII interface
Standard CSMA/CD or full duplex operation
supported
Industrial temperature compliant
LEDS
100Mb/s
TX_CLK
TXD[3:0]
TX_ER
TX_EN
Serial Management
TX Channel
Scrambler
Parallel to
Serial
NRZ To NRZI
Encoder
Binary To MLT3
Encoder
TRANSMITTER
10/100
10 TX
Filter
TXP
TXN
4B/5B
10Mb/s
NRZ To Manchester
Encoder
Link Pulse
Generator
MDIO
Interface / Controller
MDC
REGISTERS
Auto
Negotiation
Loopback
Clock
Generation
System
Clock
RXD[3:0]
RX_ER
RX_DV
RX_CLK
MII
RX Channel
100Mb/s
4B/5B
Descrambler
Code Align
Binary To MLT3
Decoder
Adaptive
Equalization
BaseLine
Wander
Serial to
Parallel
NRZI To NRZ
Decoder
Clock Recovery
RECEIVER
10/100
RXP
RXN
HW
configuration
pins
10Mb/s
HW Config
Power Down
NRZ To Manchester
Encoder
Link Pulse
Detector
10 TX Filter
Clock Recovery
SMART
Squelch
February 2006
Rev. 19
1/31
STE100P
2.2
■
■
■
■
■
■
■
■
■
Physical Layer
Integrates the whole Physical layer functions of 100Base-TX and 10Base-T
Provides Full-duplex operation on both 100Mbps and 10Mbps modes
Provides Auto-negotiation(NWAY) function of full/half duplex operation for both 10 and 100 Mbps
Provides MLT-3 transceiver with DC restoration for Base-line wander compensation
Provides transmit wave-shaper, receive filters, and adaptive equalizer
Provides loop-back modes for diagnostic
Builds in Stream Cipher Scrambler/ De-scrambler and 4B/5B encoder/decoder
Supports external transmit transformer with turn ratio 1:1
Supports external receive transformer with turn ratio 1:1
2.3 LED Display
The LED display, consists of five LEDs having the following characteristics:
■
■
■
■
■
10 Mbps Speed LED: 10Mbps(on) or 100Mbps(off)
100 Mbps Speed LED: 100Mbps(on) or 10Mbps(off)
TX/RX Activity LED: Blinks at 10Hz when receiving, but not colliding
Link LED: On when a good link is detected, blinks when there is TX or RX activity
Full Duplex / Collision LED: On during Full Duplex operation. Blinks at 20Hz to indicate a collision
Miscellaneous
2.4
■
Standard 64-pin QFP package pinout
Figure 3. System Diagram of the STE100P Application
Serial
EEPROM
LEDs
PCI Interface
MAC
Device
STE100P
STEPHY1
Transformer
RJ-45
Boot ROM
25 MHz
Crystal
2/31
STE100P
3
PIN ASSIGNMENT DIAGRAM
Figure 4. Pin Connection
rx_er/rxd4
tx_er/txd4
gnde/i
vcce/i
mdint
cfg0
cfg1
crs
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
mf4
mf3
mf2
mf1
mf0
fde
gnda
nc
vcca
gnda
x2
x1
vcca
gnda
iref
vcca
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
txn
pwrdwn
vcca
gnda
gnde
test
reset
rip
nc
nc
vcca
rxn
rxp
gnda
txp
nc
tx_en
rx_clk
tx_clk
txd3
txd2
txd1
txd0
col
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
rx_dv
rxd0
rxd1
vcce/i
rdx2
rdx3
mdc
mdio
gnde/i
vcce/i
ledr10
ledtr
ledl
ledc
leds
test_se
D99TL457B
4
PIN DESCRIPTION
Name
Type
Description
Table 2. Pin Description
Pin No.
MII Data Interface
52
58
57
56
55
54
53
txd4
txd3
txd2
txd1
txd0
tx_en
tx_clk
I
Transmit Data.
The Media Access Controller (MAC) drives data to the STE100P
using these inputs.
txd4 is monitored only in Symbol (5B) Mode.
These signals must be synchronized to the tx_clk.
Transmit Enable.
The MAC asserts this signal when it drives valid data on the
txd inputs. This signal must be synchronized to the tx_clk.
Transmit Clock.
Normally the STE100P drives tx_clk. Refer to the Clock
Requirements discussion in the Functional Description section.
25 MHz for 100 Mbps operation.
2.5 MHz for 10 Mbps operation.
I
I/O
3/31
STE100P
Table 2. Pin Description
(continued)
Pin No.
52
Name
tx_er
Type
I
Description
Transmit Coding Error.
The MAC asserts this input when an error has occurred
in the transmit data stream. When the STE100P is operating at 100 Mbps, the
STE100P responds by sending invalid code symbols on the line. In Symbol (5B)
Mode this pin functions as txd4.
Receive Data.
The STE100P drives received data on these outputs, synchro-
nous to rx_clk.
rxd4 is driven only in Symbol (5B) Mode.
51
43
44
46
47
48
51
rxd4
rxd3
rxd2
rxd1
rxd0
rx_dv
rx_er
O
O
O
Receive Data Valid.
The STE100P asserts This signal when it drives valid data
on rxd. This output is synchronous to rx_clk.
Receive Error.
The STE100P asserts this output when it receives invalid sym-
bols from the network. This signal is synchronous to rx_clk. In Symbol (5B) Mode
this pin functions as rxd4.
Receive Clock.
This continuous clock provides reference for rxd, rx_dv, and
rx_er signals. Refer to the Clock Requirements discussion in the Functional
Description section.
25 MHz for 100 Mbps operation.
2.5 MHz for 10 Mbps operation.
Collision Detected.
The STE100P asserts this output when detecting a collision.
This output remains High for the duration of the collision. This signal is asynchro-
nous and inactive during full-duplex operation.
Carrier Sense.
During half-duplex operation (PR0:8=0), the STE100P asserts
this output when either transmit or receive medium is non idle. During full duplex
operation (PR0:8=1), crs is asserted only when the receive medium is non-idle.
49
rx_clk
O
59
col
O
60
crs
O
MII Control Interface
42
41
61
mdc
mdio
mdint
I
I/O
OD
Management Data Clock.
Clock for the mdio serial data channel. Maximum
frequency is 2.5 MHz.
Management Data Input/Output,
Bi-directional serial data channel for PHY
communication.
Management Data Interrupt.
When any bit in PR18 = 1, an active High output
on this pin indicates status change in the corresponding bits in PR17.
Interrupt is cleared by reading Register PR17. Requires MDC edge to output.
Physical
(Twisted Pair) Interface
12
x1
I
25 MHz reference clock input. When an external 25 MHz crystal is used, this pin
will be connected to one terminal of it. If an external 25 MHz clock source of
oscillator is used, then this pin will be the input pin of it.
25 MHz reference clock output. When an external 25MHz crystal is used, this pin
will be connected to another terminal of if. If an external clock source is used,
then this pin should be left open.
The differential Transmit outputs of 100Base-TX or 10Base-T, these pins directly
output to the transformer.
The differential Receive inputs of 100Base-TX or 10Base-T, these pins directly
input from the transformer.
11
x2
O
21
23
19
18
txp
txn
rxp
rxn
O
I
4/31
STE100P
Table 2. Pin Description
(continued)
Pin No.
15
38
Name
iref
ledr10
Type
O
I/O
Description
Reference Resistor connecting pin for reference current, directly connect a 5KΩ ±
1% resistor to Vss.
LED display for 10Ms/s link status. This pin will be driven on continually when
10Mb/s network operating speed is detected.
The pull-up/pull-down status of this pin is latched into the PR20 bit 7 during
power up/reset.
LED display for Tx/Rx Activity status. This pin will be driven on at a 10 Hz blinking
frequency when either effective receiving or transmitting is detected.
The status of this pin is latched into the PR20 bit 6 during power up/reset.
I/O
LED display for Link Status. Blinks when there is TX or RX activity. This pin will be
driven on continually when a good Link test is detected.
The status of this pin is latched into the PR20 bit 5 during power up/reset.
LED display for Full Duplex or Collision status. This pin will be driven on
continually when a full duplex configuration is detected. This pin will be driven on
at a 20 Hz blinking frequency when a collision status is detected in the half duplex
configuration.
The status of this pin is latched into the PR20 bit 4 during power up/reset.
LED display for 100Ms/s link status. This pin will be driven on continually when
100Mb/s network operating speed is detected.
The status of this pin is latched into the PR20 bit 3 during power up/reset.
Configuration Control 0.
When A/N is enabled,
cfg0 determines operating mode advertisement
capabilities in combination with cfg1 when mf0/ PR0:12 =1. (See Table 2)
When A/N is disabled,
cfg1 disables mlt3 and directly affects PR19:0
When cfg0 is Low, mlt3 encoder/decoder is enabled and PR19:1 =0.
When cfg0 is High, mlt3 encoder/decoder is bypassed and PR19:1 = 1.
Configuration Control 1.
When A/N is enabled,
cfg1 determines operating mode advertisement
capabilities in combination with cfg1 when mf0/ PR0:12 =1. (See Table 2)
When A/N is disabled,
CFG1 enables Loopback mode and directly affects PR0
bit 14.
When cfg1 is Low, Loopback mode is disabled and PR0:14 = 0.
When cfg1 is High, Loopback mode is enabled and PR0:14 = 1.
Reset
(Active-Low). This input must be held low for a minimum of 1 ms to reset
the STE100P. During Power-up, the STE100P will be reset regardless of the state
of this pin, and this reset will not be complete until after >1ms.
Reset In Progress.
This output is used to indicate when the device has
completed power-up/reset and the registers and functions can be accessed.
When rip is High, power-up/reset has been successful and the device can be
used normally
When rip is Low, device reset is not complete.
nc (No Connection)
Test pins. Should be tied to ground for normal operation
I
Power Down.
When High, forces STE100P into Power Down mode. This pin is
OR’ed with the Power Down bit (PR0:11). During the Power Down mode, txp/txn
outputs and all LED outputs are 3-stated, and the MII interface is isolated.
37
ledtr
36
ledl
35
ledc
I/O
34
leds
I/O
64
cfg0
I
63
cfg1
I
28
reset
I
29
rip
O
8, 30,31,
32
26, 33
27
nc
test,
test_se
pwrdwn
5/31
京公网安备 11010802033920号
EEWORLD
