MLD2N06CL
Preferred Device
SMARTDISCRETESt MOSFET
2 Amp, 62 Volts, Logic Level
N−Channel DPAK
The MLD2N06CL is designed for applications that require a rugged
power switching device with short circuit protection that can be
directly interfaced to a microcontrol unit (MCU). Ideal applications
include automotive fuel injector driver, incandescent lamp driver or
other applications where a high in−rush current or a shorted load
condition could occur.
This Logic Level Power MOSFET features current limiting for
short circuit protection, integrated Gate−Source clamping for ESD
protection and integral Gate−Drain clamping for over−voltage
protection and SENSEFETt technology for low on−resistance. No
additional gate series resistance is required when interfacing to the
output of a MCU, but a 40 kW gate pulldown resistor is recommended
to avoid a floating gate condition.
The internal Gate−Source and Gate−Drain clamps allow the device
to be applied without use of external transient suppression
components. The Gate−Source clamp protects the MOSFET input
from electrostatic voltage stress up to 2.0 kV. The Gate−Drain clamp
protects the MOSFET drain from the avalanche stress that occurs with
inductive loads. Their unique design provides voltage clamping that is
essentially independent of operating temperature.
Features
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V
(BR)DSS
62 V (Clamped)
R
DS(on)
TYP
400 mW
I
D
MAX
2.0 A
N−Channel
D
R1
G
R2
S
•
Pb−Free Packages are Available
MAXIMUM RATINGS
(T
J
= 25°C unless otherwise noted)
Rating
Drain−to−Source Voltage
Drain−to−Gate Voltage (R
GS
= 1.0 MW)
Gate−to−Source Voltage
−
Continuous
Drain Current
−
Continuous @ T
C
= 25°C
Total Power Dissipation @ T
C
= 25°C
Electrostatic Voltage
Operating & Storage Temperature Range
Symbol
V
DSS
V
DGR
V
GS
I
D
P
D
ESD
T
J
, T
stg
T
J(max)
R
qJC
R
qJA
R
qJA
T
L
Value
Clamped
Clamped
±10
Self−limited
40
2.0
−50
to 150
Unit
Vdc
Vdc
Vdc
Adc
W
kV
°C
Y
WW
L2N06CL
G
1 2
3
4
CASE 369C
DPAK
STYLE 2
MARKING
DIAGRAM
YWW
L2N
06CLG
= Year
= Work Week
= Device Code
= Pb−Free Package
ORDERING INFORMATION
Device
Package
DPAK
DPAK
(Pb−Free)
DPAK
DPAK
(Pb−Free)
Shipping
†
75 Units/Rail
75 Units/Rail
2500 Tape & Reel
2500 Tape & Reel
THERMAL CHARACTERISTICS
Maximum Junction Temperature
Thermal Resistance,
Junction−to−Case
Junction−to−Ambient (Note 1)
Junction−to−Ambient (Note 2)
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 5 seconds
150
3.12
100
71.4
260
°C
°C/W
MLD2N06CL
MLD2N06CLG
MLD2N06CLT4
°C
MLD2N06CLT4G
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. When surface mounted to an FR−4 board using the minimum recommended
pad size.
2. When surface mounted to an FR−4 board using the 0.5 sq.in. drain pad size.
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Preferred
devices are recommended choices for future use
and best overall value.
©
Semiconductor Components Industries, LLC, 2009
October, 2009
−
Rev. 3
1
Publication Order Number:
MLD2N06CL/D
MLD2N06CL
DRAIN−TO−SOURCE AVALANCHE CHARACTERISTICS
Rating
Single Pulse Drain−to−Source Avalanche Energy
(Starting T
J
= 25°C, I
D
= 2.0 A, L = 40 mH)
Symbol
E
AS
Value
80
Unit
mJ
ELECTRICAL CHARACTERISTICS
(T
C
= 25°C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage (Internally Clamped)
(I
D
= 20 mAdc, V
GS
= 0 Vdc)
(I
D
= 20 mAdc, V
GS
= 0 Vdc, T
J
= 150°C)
Zero Gate Voltage Drain Current
(V
DS
= 40 Vdc, V
GS
= 0 Vdc)
(V
DS
= 40 Vdc, V
GS
= 0 Vdc, T
J
= 150°C)
Gate−Source Leakage Current
(V
G
= 5.0 Vdc, V
DS
= 0 Vdc)
(V
G
= 5.0 Vdc, V
DS
= 0 Vdc, T
J
= 150°C)
ON CHARACTERISTICS
(Note 3)
Gate Threshold Voltage
(I
D
= 250
mAdc,
V
DS
= V
GS
)
(I
D
= 250
mAdc,
V
DS
= V
GS
, T
J
= 150°C)
Static Drain Current Limit
(V
GS
= 5.0 Vdc, V
DS
= 10 Vdc)
(V
GS
= 5.0 Vdc, V
DS
= 10 Vdc, T
J
= 150°C)
Static Drain−to−Source On−Resistance
(I
D
= 1.0 Adc, V
GS
= 5.0 Vdc)
(I
D
= 1.0 Adc, V
GS
= 5.0 Vdc, T
J
= 150°C)
Forward Transconductance (I
D
= 1.0 Adc, V
DS
= 10 Vdc)
Static Source−to−Drain Diode Voltage (I
S
= 1.0 Adc, V
GS
= 0 Vdc)
RESISTIVE SWITCHING CHARACTERISTICS
(Note 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
3. Pulse Test: Pulse Width
≤
300
ms,
Duty Cycle
≤
2%.
4. Switching characteristics are independent of operating junction temperature.
5
4.0
I D , DRAIN CURRENT (AMPS)
6.0 V
5.5 V
5.0 V
4.5 V
4.0 V
3.5 V
3.0 V
2
3.5
T
J
= 150°C
3.0
2.5
2.0
1.5
1.0
0.5
6
8
0
0
1
2
3
4
5
6
7
8
V
DS
≥
7.5 V
(V
DD
= 30 Vdc, I
D
= 1.0 Adc,
V
GS(on)
= 5.0 Vdc, R
GS
= 25W)
t
d(on)
t
r
t
d(off)
t
f
−
−
−
−
1.0
3.0
5.0
3.0
1.5
5.0
8.0
5.0
ms
V
GS(th)
1.0
0.6
3.8
1.6
−
−
1.0
−
1.5
1.0
4.4
2.4
0.3
0.53
1.4
1.1
2.0
1.6
5.2
2.9
0.4
0.7
−
1.5
Vdc
V
(BR)DSS
58
58
−
−
−
−
62
62
0.6
6.0
0.5
1.0
66
66
5.0
20
5.0
20
Vdc
Symbol
Min
Typ
Max
Unit
I
DSS
mAdc
I
GSS
mAdc
I
D(lim)
Adc
R
DS(on)
W
g
FS
V
SD
mhos
Vdc
T
J
= 25°C
- 55°C
25°C
I D , DRAIN CURRENT (AMPS)
4
3
1
2.5 V
2.0 V
0
0
2
4
V
DS
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
V
GS
, GATE-TO-SOURCE VOLTAGE (VOLTS)
Figure 1. Output Characteristics
Figure 2. Transfer Function
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MLD2N06CL
THE SMARTDISCRETES CONCEPT
From a standard power MOSFET process, several active
and passive elements can be obtained that provide on−chip
protection to the basic power device. Such elements require
only a small increase in silicon area and/or the addition of one
masking layer to the process. The resulting device exhibits
significant improvements in ruggedness and reliability as
well as system cost reduction. The SMARTDISCRETES
device functions can now provide an economical alternative
to smart power ICs for power applications requiring low
on−resistance, high voltage and high current.
These devices are designed for applications that require a
rugged power switching device with short circuit protection
that can be directly interfaced to a microcontroller unit
(MCU). Ideal applications include automotive fuel injector
driver, incandescent lamp driver or other applications where
a high in−rush current or a shorted load condition could occur.
OPERATION IN THE CURRENT LIMIT MODE
SHORT CIRCUIT PROTECTION AND THE EFFECT OF
TEMPERATURE
The amount of time that an unprotected device can
withstand the current stress resulting from a shorted load
before its maximum junction temperature is exceeded is
dependent upon a number of factors that include the amount
of heatsinking that is provided, the size or rating of the
device, its initial junction temperature, and the supply
voltage. Without some form of current limiting, a shorted
load can raise a device’s junction temperature beyond the
maximum rated operating temperature in only a few
milliseconds.
Even with no heatsink, the MLD2N06CL can withstand
a shorted load powered by an automotive battery (10 to 14
V) for almost a second if its initial operating temperature is
under 100°C. For longer periods of operation in the
current−limited mode, device heatsinking can extend
operation from several seconds to indefinitely depending on
the amount of heatsinking provided.
The on−chip circuitry of the MLD2N06CL offers an
integrated means of protecting the MOSFET component
from high in−rush current or a shorted load. As shown in the
schematic diagram, the current limiting feature is provided
by an NPN transistor and integral resistors R1 and R2. R2
senses the current through the MOSFET and forward biases
the NPN transistor’s base as the current increases. As the
NPN turns on, it begins to pull gate drive current through R1,
dropping the gate drive voltage across it, and thus lowering
the voltage across the gate−to−source of the power
MOSFET and limiting the current. The current limit is
temperature dependent as shown in Figure 3, and decreases
from about 2.3 amps at 25°C to about 1.3 A at 150°C.
Since the MLD2N06CL continues to conduct current and
dissipate power during a shorted load condition, it is
important to provide sufficient heatsinking to limit the
device junction temperature to a maximum of 150°C.
The metal current sense resistor R2 adds about 0.4 ohms
to the power MOSFET’s on−resistance, but the effect of
temperature on the combination is less than on a standard
MOSFET due to the lower temperature coefficient of R2.
The on−resistance variation with temperature for gate
voltages of 4 and 5 V is shown in Figure 5.
Back−to−back polysilicon diodes between gate and
source provide ESD protection to greater than 2 kV, HBM.
This on−chip protection feature eliminates the need for an
external Zener diode for systems with potentially heavy line
transients.
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3
MLD2N06CL
6
5
4
3
2
1
0
RDS(on) , ON-RESISTANCE (OHMS)
I D(lim) , DRAIN CURRENT (AMPS)
V
GS
= 5 V
V
DS
= 10 V
1.0
I
D
= 1 A
0.8
0.6
100°C
25°C
0.2
T
J
= - 50°C
7
8
4
5
6
3
V
GS
, GATE-TO-SOURCE VOLTAGE (VOLTS)
2
0.4
- 50
0
50
100
150
0
0
1
9
10
T
J
, JUNCTION TEMPERATURE (°C)
Figure 3. I
D(lim)
Variation
With Temperature
Figure 4. R
DS(on)
Variation With
Gate−To−Source Voltage
0.6
RDS(on) , ON-RESISTANCE (OHMS)
I
D
= 1 A
0.5
0.4
0.3
0.2
0.1
0
- 50
V
GS
= 4 V
V
GS
= 5 V
0
50
100
T
J
, JUNCTION TEMPERATURE (°C)
150
Figure 5. On−Resistance Variation With
Temperature
BV(DSS) , DRAIN-TO-SOURCE SUSTAINING VOLTAGE (V)
100
EAS , SINGLE PULSE DRAIN-TO-SOURCE
AVALANCHE ENERGY (mJ)
I
D
= 2 A
80
64.0
63.5
63.0
62.5
62.0
61.5
61.0
60.5
60.0
- 50
0
50
100
T
J
= JUNCTION TEMPERATURE
150
I
D
= 20 mA
60
40
20
0
25
50
75
100
125
T
J
, STARTING JUNCTION TEMPERATURE (°C)
150
Figure 6. Maximum Avalanche Energy
versus Junction Temperature
Figure 7. Drain−Source Sustaining
Voltage Variation With Temperature
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MLD2N06CL
FORWARD BIASED SAFE OPERATING AREA
The FBSOA curves define the maximum drain−to−source
voltage and drain current that a device can safely handle
when it is forward biased, or when it is on, or being turned
on. Because these curves include the limitations of
simultaneous high voltage and high current, up to the rating
of the device, they are especially useful to designers of linear
systems. The curves are based on a case temperature of 25°C
and a maximum junction temperature of 150°C. Limitations
for repetitive pulses at various case temperatures can be
determined by using the thermal response curves.
ON Semiconductor Application Note, AN569, “Transient
Thermal Resistance
−
General Data and Its Use” provides
detailed instructions.
MAXIMUM DC VOLTAGE CONSIDERATIONS
(1.8 A at 150°C) and not the R
DS(on)
. The maximum
voltage can be calculated by the following equation:
V
supply
=
(150
−
T
A
)
I
D(lim)
(R
qJC
+ R
qCA
)
where the value of R
qCA
is determined by the heatsink that
is being used in the application.
DUTY CYCLE OPERATION
When operating in the duty cycle mode, the maximum
drain voltage can be increased. The maximum operating
temperature is related to the duty cycle (DC) by the
following equation:
T
C
= (V
DS
x I
D
x DC x R
qCA
) + T
A
The maximum drain−to−source voltage that can be
continuously applied across the MLD2N06CL when it is
in current limit is a function of the power that must be
dissipated. This power is determined by the maximum
current limit at maximum rated operating temperature
10
V
GS
= 10 V
SINGLE PULSE
T
C
= 25°C
The maximum value of V
DS
applied when operating in a
duty cycle mode can be approximated by:
V
DS
=
150
−
T
C
I
D(lim)
x DC x R
qJC
ID , DRAIN CURRENT (AMPS)
1.0
dc
10 ms
1 ms
R
DS(on)
LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.1
1.0
10
V
DS
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
100
Figure 8. Maximum Rated Forward Bias
Safe Operating Area (MLD2N06CL)
1.0
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
D = 0.5
0.2
0.1
0.1 0.05
0.02
0.01
SINGLE PULSE
0.01
1.0E - 05
1.0E - 04
1.0E - 03
1.0E - 02
t, TIME (s)
P
(pk)
R
qJC
(t) = r(t) R
qJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
1
T
J(pk)
- T
C
= P
(pk)
R
qJC
(t)
t
1
t
2
DUTY CYCLE, D = t
1
/t
2
1.0E - 01
1.0E+00
1.0E+01
Figure 9. Thermal Response (MLD2N06CL)
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