MM74HC240 Inverting Octal 3-STATE Buffer
September 1983
Revised May 2005
MM74HC240
Inverting Octal 3-STATE Buffer
General Description
The MM74HC240 3-STATE buffer utilizes advanced sili-
con-gate CMOS technology. It possesses high drive cur-
rent outputs which enable high speed operation even when
driving large bus capacitances. These circuits achieve
speeds comparable to low power Schottky devices, while
retaining the advantage of CMOS circuitry, i.e., high noise
immunity and low power consumption. It has a fanout of 15
LS-TTL equivalent inputs.
The MM74HC240 is an inverting buffer and has two active
LOW enables (1G and 2G). Each enable independently
controls 4 buffers.
All inputs are protected from damage due to static dis-
charge by diodes to V
CC
and ground.
Features
s
Typical propagation delay: 12 ns
s
3-STATE outputs for connection to system buses
s
Wide power supply range: 2–6V
s
Low quiescent supply current: 80
P
A (74 Series)
s
Output current: 6 mA
Ordering Code:
Order Number
MM74HC240WM
MM74HC240SJ
MM74HC240MTC
MM74HC240N
Package Number
M20B
M20D
MTC20
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Truth Table
1G
L
L
H
H
H HIGH Level
L LOW Level
Z HIGH Impedance
1A
L
H
L
H
1Y
H
L
Z
Z
2G
L
L
H
H
2A
L
H
L
H
2Y
H
L
Z
Z
Top View
© 2005 Fairchild Semiconductor Corporation
DS005020
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MM74HC240
Logic Diagram
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2
MM74HC240
Absolute Maximum Ratings
(Note 1)
(Note 2)
Supply Voltage (V
CC
)
Recommended Operating
Conditions
Min
Supply Voltage (V
CC
)
DC Input or Output Voltage
(V
IN
, V
OUT
)
Operating Temperature Range (T
A
)
Input Rise or Fall Times
(t
r
, t
f
) V
CC
V
CC
4.5V
6.0V
V
CC
2.0V
1000
500
400
ns
ns
ns
2
0
Max
6
V
CC
Units
V
V
0.5 to
7.0V
1.5 to V
CC
1.5V
DC Input Voltage (V
IN
)
DC Output Voltage (V
OUT
)
0.5 to V
CC
0.5V
Clamp Diode Current (I
IK
, I
OK
)
r
20 mA
r
35 mA
DC Output Current, per pin (I
OUT
)
DC V
CC
or GND Current, per pin (I
CC
)
r
70 mA
Storage Temperature Range (T
STG
)
65
q
C to
150
q
C
(Note 3)
S.O. Package only
600 mW
500 mW
260
q
C
40
85
q
C
Power Dissipation (P
D
)
Lead Temperature (T
L
)
(Soldering 10 seconds)
Note 1:
Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Note 2:
unless otherwise specified all voltages are referenced to ground.
Note 3:
Power Dissipation temperature derating — plastic “N” package:
12 mW/
q
C from 65
q
C to 85
q
C.
DC Electrical Characteristics
Symbol
V
IH
Parameter
Minimum HIGH Level
Input Voltage
V
IL
Maximum LOW Level
Input Voltage
V
OH
Minimum HIGH Level
Output Voltage
V
I N
V
IH
or V
IL
Conditions
(Note 4)
V
CC
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
T
A
Typ
1.5
3.15
4.2
0.5
1.35
1.8
2.0
4.5
6.0
4.2
5.7
0
0
0
0.2
0.2
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
25
q
C
T
A
40 to 85
q
C T
A
55 to 125
q
C
Guaranteed Limits
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
Units
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
|I
OUT
|
d
20
P
A
2.0V
4.5V
6.0V
V
IN
V
IH
or V
IL
4.5V
6.0V
2.0V
4.5V
6.0V
|I
OUT
|
d
6.0 mA
|I
OUT
|
d
7.8 mA
V
OL
Maximum LOW Level
Output Voltage
V
IN
V
IH
or V
IL
|I
OUT
|
d
20
P
A
V
IN
V
IH
or V
IL
4.5V
6.0V
6.0V
6.0V
|I
OUT
|
d
6.0 mA
|I
OUT
|
d
7.8 mA
I
IN
I
OZ
Maximum Input Current
Maximum 3-STATE
Output Leakage
Current
I
CC
Maximum Quiescent
Supply Current
V
IN
V
IN
V
OUT
G
V
IN
I
OUT
V
CC
or GND
V
IH
or V
IL
V
CC
or GND
V
IL
V
CC
or GND
0
P
A
r
0.1
r
0.5
r
1.0
r
5
r
1.0
r
10
P
A
P
A
V
IH
, G
6.0V
8.0
80
160
P
A
Note 4:
For a power supply of 5V
r
10% the worst case output voltages (V
OH
, and V
OL
) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case V
IH
and V
IL
occur at V
CC
5.5V and 4.5V respectively. (The V
IH
value at 5.5V is 3.85V.) The worst case leakage cur-
rent (I
IN
, I
CC
, and I
OZ
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
3
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MM74HC240
AC Electrical Characteristics
V
CC
5V, T
A
25
q
C, t
r
t
f
6 ns
Conditions
C
L
R
L
C
L
R
L
C
L
45 pF
1 k
:
45 pF
1 k
:
5 pF
Typ
12
14
13
Guaranteed Limit
18
28
25
Units
ns
ns
ns
Symbol
t
PHL
, t
PLH
t
PZH
, t
PZL
t
PHZ
, t
PLZ
Parameter
Maximum Propagation Delay
Maximum Enable Delay
to Active Output
Maximum Disable Delay
from Active Output
AC Electrical Characteristics
V
CC
2.0V to 6.0V, C
L
50 pF, t
r
t
f
6 ns (unless otherwise specified)
Conditions
C
L
C
L
C
L
C
L
C
L
C
L
t
PZH
, t
PZL
Maximum Output Enable
TIme
R
L
C
L
C
L
C
L
C
L
C
L
C
L
t
PHZ
, t
PLZ
Maximum Output Disable
Time
t
TLH
, t
THL
Maximum Output
Rise and Fall Time
C
PD
Power Dissipation
Capacitance (Note 5)
C
IN
C
OUT
Maximum Input Capacitance
Maximum Output Capacitance
(per buffer)
G
G
V
IH
V
IL
12
50
5
10
10
20
10
20
10
20
pF
pF
pF
pF
R
L
C
L
50 pF
150 pF
50 pF
150 pF
50 pF
150 pF
1 k
:
50 pF
150 pF
50 pF
150 pF
50 pF
150 pF
1 k
:
50 pF
2.0V
2.0V
4.5V
4.5V
6.0V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
75
100
15
20
13
17
75
15
13
150
200
30
40
26
34
150
30
26
60
12
10
189
252
38
50
32
43
189
38
32
75
15
13
224
298
45
60
38
51
224
45
38
90
18
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
CC
2.0V
2.0V
4.5V
4.5V
6.0V
6.0V
T
A
Typ
55
80
12
22
11
28
100
150
20
30
17
26
25
q
C
T
A
Symbol
Parameter
40 to 85
q
C T
A
55 to 125
q
C
Guaranteed Limits
126
190
25
38
21
32
149
224
30
45
25
38
Units
ns
ns
ns
ns
ns
ns
t
PHL
, t
PLH
Maximum Propagation
Delay
Note 5:
C
PD
determines the no load dynamic power consumption, P
D
I
S
C
PD
V
CC
f
I
CC
.
C
PD
V
CC2
f
I
CC
V
CC
, and the no load dynamic current consumption,
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4
MM74HC240
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
5
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