MC100EL38
5 V ECL
÷2, ÷4/6
Clock
Generation Chip
Description
The MC100EL38 is a low skew
÷2, ÷4/6
clock generation chip
designed explicitly for low skew clock generation applications. The
internal dividers are synchronous to each other, therefore, the common
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output edges are all precisely aligned. The device can be driven by
either a differential or single-ended ECL or, if positive power supplies
are used, PECL input signal.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
SOIC−20 WB
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
DW SUFFIX
and V
CC
via a 0.01
mF
capacitor and limit current sourcing or sinking
CASE 751D−05
to 0.5 mA. When not used, V
BB
should be left open.
The common enable (EN) is synchronous so that the internal
dividers will only be enabled/disabled when the internal clock is
MARKING DIAGRAM*
already in the LOW state. This avoids any chance of generating a runt
20
clock pulse on the internal clock when the device is enabled/disabled
as can happen with an asynchronous control. An internal runt pulse
could lead to losing synchronization between the internal divider
100EL38
AWLYYWWG
stages. The internal enable flip-flop is clocked on the falling edge of
the input clock, therefore, all associated specification limits are
referenced to the negative edge of the clock input.
1
The Phase_Out output will go HIGH for one clock cycle whenever
A
= Assembly Location
the
÷2
and the
÷4/6
outputs are both transitioning from a LOW to a
WL
= Wafer Lot
HIGH. This output allows for clock synchronization within the system.
YY
= Year
Upon startup, the internal flip-flops will attain a random state;
WW
= Work Week
therefore, for systems which utilize multiple EL38s, the master reset
G
= Pb-Free Package
(MR) input must be asserted to ensure synchronization. For systems
*For additional marking information, refer to
which only use one EL38, the MR pin need not be exercised as the
Application Note
AND8002/D.
internal divider design ensures synchronization between the
÷2
and
the
÷4/6
outputs of a single device.
•
50 ps Output-to-Output Skew
ORDERING INFORMATION
•
Synchronous Enable/Disable
Device
Package
Shipping
†
•
Master Reset for Synchronization
MC100EL38DWR2G SOIC−20 WB 1000/Tape & Reel
•
ESD Protection:
(Pb-Free)
♦
2 kV Human Body Model
♦
100 V Machine Model
†For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
•
The 100 Series Contains Temperature Compensation
to our Tape and Reel Packaging Specifications
•
PECL Mode Operating Range:
Brochure,
BRD8011/D.
♦
V
CC
= 4.2 V to 5.7 V with V
EE
= 0 V
•
NECL Mode Operating Range:
•
Moisture Sensitivity Level: 3 (Pb-Free)
♦
V
CC
= 0 V with V
EE
=
−4.2
V to
−5.7
V
♦
For Additional Information, see Application Note
AND8003/D
•
Internal 75 kW Input Pulldown Resistors on CLK, EN,
•
Flammability Rating:
MR, and DIVSEL
♦
UL 94 V−0 @ 0.125 in, Oxygen Index: 28 to 34
•
Q Output will Default LOW with Inputs Open or at
•
Transistor Count = 388 devices
V
EE
•
Meets or Exceeds JEDEC Spec EIA/JESD78 IC
•
These Devices are Pb-Free, Halogen Free and are
Latchup Test
RoHS Compliant
©
Semiconductor Components Industries, LLC, 2016
July, 2016
−
Rev. 9
1
Publication Order Number:
MC100EL38/D
MC100EL38
V
CC
20
Q0
19
Q0
18
Q1
17
Q1
16
Q2
15
Q2
14
Q3
13
Q3
12
V
EE
11
1
V
CC
2
3
4
5
CLK
6
V
BB
7
MR
8
9
10
EN DIV_SEL CLK
V
CC
Phase_Out Phase_Out
* All V
CC
pins are tied together on the die.
Warning: All V
CC
and V
EE
pins must be externally connected
to Power Supply to guarantee proper operation.
Figure 1. Pinout Assignment
(Top View)
Q0
CLK
CLK
P2
R
Q0
Q1
Q1
Q2
R
P4/6
R
MR
DIVSEL
Phase
Out
Logic
R
PHASE_OUT
PHASE_OUT
Q2
Q3
Q3
EN
Figure 2. Logic Diagram
Table 1. PIN DESCRIPTION
Pin
CLK, CLK
Q
0
, Q
1;
Q
0
, Q
1
Q
2
, Q
3;
Q
2
, Q
3
EN
MR
DIVSEL
Phase_Out, Phase_Out
V
BB
V
CC
V
EE
Function
ECL Diff Clock Inputs
ECL Diff
÷2
Outputs
ECL Diff
÷4/6
Outputs
ECL Sync Enable Input
ECL Master Reset Input
ECL Frequency Select Input
ECL Phase Sync Diff. Signal Output
Reference Voltage Output
Positive Supply
Negative Supply
Table 2. FUNCTION TABLE
CLK
Z
ZZ
X
EN
L
H
X
MR
L
L
H
Function
Divide
Hold Q
0−3
Reset Q
0−3
Z = Low-to-High Transition
ZZ = High-to-Low Transition
X = Don’t Care
DIVSEL
L
H
Q
2
, Q
3
OUTPUTS
Divide by 4
Divide by 6
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2
MC100EL38
Table 3. MAXIMUM RATINGS
Symbol
V
CC
V
EE
V
I
I
out
I
BB
T
A
T
stg
q
JA
q
JC
T
sol
Parameter
PECL Mode Power Supply
NECL Mode Power Supply
PECL Mode Input Voltage
NECL Mode Input Voltage
Output Current
V
BB
Sink/Source
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction-to-Ambient)
Thermal Resistance (Junction-to-Case)
Wave Solder (Pb-Free)
0 lfpm
500 lfpm
Standard Board
<2 to 3 sec @ 260°C
SOIC−20 WB
SOIC−20 WB
Condition 1
V
EE
= 0 V
V
CC
= 0 V
V
EE
= 0 V
V
CC
= 0 V
Continuous
Surge
V
I
≤
V
CC
V
I
≥
V
EE
Condition 2
Rating
8
−8
6
−6
50
100
±
0.5
−40
to +85
−65
to +150
90
60
30 to 35
265
Unit
V
V
V
MA
mA
°C
°C
°C/W
°C/W
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
Table 4. 100EL SERIES PECL DC CHARACTERISTICS
(V
CC
= 5.0 V; V
EE
= 0.0 V (Note 1))
−40°C
Symbol
I
EE
V
OH
V
OL
V
IH
V
IL
V
BB
V
IHCMR
I
IH
I
IL
Characteristic
Power Supply Current
Output HIGH Voltage (Note 2)
Output LOW Voltage (Note 2)
Input HIGH Voltage (Single-Ended)
Input LOW Voltage (Single-Ended)
Output Voltage Reference
Input HIGH Voltage Common Mode
Range (Differential) (Note 3)
Input HIGH Current
Input LOW Current
0.5
3915
3170
3835
3190
3.62
1.65
Min
Typ
50
3995
3305
Max
60
4120
3445
4120
3525
3.74
4.45
150
0.5
3975
3190
3835
3190
3.62
1.65
Min
25°C
Typ
50
4045
3295
Max
60
4120
3380
4120
3525
3.74
4.45
150
0.5
3975
3190
3835
3190
3.62
1.65
Min
85°C
Typ
54
4050
3295
Max
65
4120
3380
4120
3525
3.74
4.45
150
Unit
mA
mV
mV
mV
mV
V
V
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.8 V /
−0.5
V.
2. Outputs are terminated through a 50
W
resistor to V
CC
−
2.0 V.
3. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential input
signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between V
PP
min and 1 V.
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3
MC100EL38
Table 5. 100EL SERIES NECL DC CHARACTERISTICS
(V
CC
= 0.0 V; V
EE
=
−5.0
V (Note 1))
−40°C
Symbol
I
EE
V
OH
V
OL
V
IH
V
IL
V
BB
V
IHCMR
I
IH
I
IL
Characteristic
Power Supply Current
Output HIGH Voltage (Note 2)
Output LOW Voltage (Note 2)
Input HIGH Voltage (Single-Ended)
Input LOW Voltage (Single-Ended)
Output Voltage Reference
Input HIGH Voltage Common Mode
Range (Differential) (Note 3)
Input HIGH Current
Input LOW Current
0.5
−1085
−1830
−1165
−1810
−1.38
−3.35
Min
Typ
50
−1005
−1695
Max
60
−880
−1555
−880
−1475
−1.26
−0.55
150
0.5
−1025
−1810
−1165
−1810
−1.38
−3.35
Min
25°C
Typ
50
−955
−1705
Max
60
−880
−1620
−880
−1475
−1.26
−0.55
150
0.5
−1025
−1810
−1165
−1810
−1.38
−3.35
Min
85°C
Typ
54
−955
−1705
Max
65
−880
−1620
−880
−1475
−1.26
−0.55
150
Unit
mA
mV
mV
mV
mV
V
V
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.8 V /
−0.5
V.
2. Outputs are terminated through a 50
W
resistor to V
CC
−
2.0 V.
3. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential input
signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between V
PP
min and 1 V.
Table 6. AC CHARACTERISTICS
(V
CC
= 5.0 V; V
EE
= 0.0 V or V
CC
= 0.0 V; V
EE
=
−5.0
V (Note 1)
−40°C
Symbol
f
max
t
PLH
t
PHL
Characteristic
Maximum Toggle Frequency
Propagation Delay to Output
CLK
→
Q (Differential)
CLK
→
Q (Single-Ended)
CLK
→
Phase_Out (Differential)
CLK
→
Phase_Out (Single-Ended)
MR
→
Q
Within-Device Skew (Note 2)
Q
0
−
Q
3
All
Cycle-to-Cycle Jitter
Part-to-Part
Q
0
−
Q
3
(Differential)
All
t
S
Setup Time
EN
→
CLK
DIVSEL
→
CLK
Hold Time
CLK
→
EN
CLK
→
Div_Sel
Input Swing (Note 3)
Reset Recovery Time
Minimum Pulse Width
CLK
MR
Output Rise/Fall Times Q (20%
−
80%)
800
700
280
550
150
150
TBD
200
240
150
810
710
800
750
510
Min
Typ
TBD
1010
1010
1000
1050
810
50
75
TBD
200
240
150
850
750
840
790
540
Max
Min
25°C
Typ
TBD
1050
1050
1040
1090
840
50
75
TBD
200
240
ps
900
800
890
840
570
Max
Min
85°C
Typ
TBD
1100
1100
1090
1140
870
50
75
Max
Unit
GHz
ps
t
SKEW
ps
t
JITTER
ps
t
H
150
200
1000
100
800
700
280
150
150
200
1000
100
800
700
550
280
150
150
200
1000
100
ps
V
PP
t
RR
t
PW
mV
ps
ps
t
r
, t
f
550
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. V
EE
can vary +0.8 V /
−0.5
V.
2. Skew is measured between outputs under identical transitions.
3. V
PP(
min) is minimum input swing for which AC parameters guaranteed. The device has a DC gain of
≈40.
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4
MC100EL38
t
RR
MR
CLK
Q (P2)
Q (P4)
Q (P6)
Phase_Out (P4)
Phase_Out (P6)
Figure 3. Timing Diagram
Q
Driver
Device
Q
Z
o
= 50
W
D
Receiver
Device
Z
o
= 50
W
50
W
50
W
D
V
TT
V
TT
= V
CC
−
2.0 V
Figure 4. Typical Termination for Output Driver and Device Evaluation
(See Application Note
AND8020/D
−
Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
−
ECL Clock Distribution Techniques
−
Designing with PECL (ECL at +5.0 V)
−
ECLinPS I/O SPiCE Modeling Kit
−
Metastability and the ECLinPS Family
−
Interfacing Between LVDS and ECL
−
The ECL Translator Guide
−
Odd Number Counters Design
−
Marking and Date Codes
−
Termination of ECL Logic Devices
−
Interfacing with ECLinPS
−
AC Characteristics of ECL Devices
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