a
FEATURES
14-Bit, 40/65 MSPS ADC
Low Power:
550 mW at 65 MSPS
300 mW at 40 MSPS
On-Chip Reference and Sample-and-Hold
750 MHz Analog Input Bandwidth
SNR > 73 dBc to Nyquist @ 65 MSPS
SFDR > 86 dBc to Nyquist @ 65 MSPS
Differential Nonlinearity Error = 0.7 LSB
Guaranteed No Missing Codes over Full Temperature Range
1 V to 2 V p-p Differential Full-Scale Analog Input Range
Single 5 V Analog Supply, 3.3 V/5 V Driver Supply
Out-of-Range Indicator
Straight Binary or Twos Complement Output Data
Clock Duty Cycle Stabilizer
Output Enable Function
48-Lead LQFP Package
APPLICATIONS
Communications Subsystems (Microcell, Picocell)
Medical and High End Imaging Equipment
Ultrasound Equipment
GENERAL DESCRIPTION
14-Bit, 40/65 MSPS A/D Converter
AD9244
FUNCTIONAL BLOCK DIAGRAM
AVDD
REFT REFB
DRVDD
AD9244
VIN+
SHA
VIN–
TEN
STAGE
PIPELINE
ADC
DFS
14
CLK+
CLK–
TIMING
OUTPUT
REGISTER
OTR
DCS
D13–D0
14
REFERENCE
OEB
AGND CML VR
VREF SENSE
REF
GND
DGND
PRODUCT HIGHLIGHTS
The AD9244 is a monolithic, single 5 V supply, 14-bit,
40 MSPS/65 MSPS analog-to-digital converter with an on-chip,
high performance sample-and-hold amplifier and voltage reference.
The AD9244 uses a multistage differential pipelined architecture
with output error correction logic to provide 14-bit accuracy at
40 MSPS/65 MSPS data rates and guarantees no missing codes
over the full operating temperature range.
The AD9244 has an on-board, programmable voltage reference.
An external reference can also be used to suit the dc accuracy
and temperature drift requirements of the application.
A differential or single-ended clock input is used to control all
internal conversion cycles. The digital output data can be pre-
sented in straight binary or in twos complement format. An
out-of-range (OTR) signal indicates an overflow condition that
can be used with the most significant bit to determine low or
high overflow.
Fabricated on an advanced CMOS process, the AD9244 is
available in a 48-lead low profile quad flatpack package (LQFP)
and is specified for operation over the industrial temperature
range (–40°C to +85°C).
Low Power—The
AD9244, at 550 mW, consumes a frac-
tion of the power of presently available ADCs in existing
high speed solutions.
IF Sampling—The
AD9244 delivers outstanding perfor-
mance at input frequencies beyond the first Nyquist zone.
Sampling at 65 MSPS with an input frequency of 100 MHz,
the AD9244 delivers 71 dB SNR and 86 dB SFDR.
Pin Compatibility—The
AD9244 offers a seamless
migration from the 12-bit, 65 MSPS AD9226.
On-Board Sample-and-Hold (SHA)—The
versatile SHA
input can be configured for either single-ended or differ-
ential inputs.
Out-of-Range (OTR)—The
OTR output bit indicates
when the input signal is beyond the AD9244’s input range.
Single Supply—The
AD9244 uses a single 5 V power
supply, simplifying system power supply design. It also
features a separate digital output driver supply to accom-
modate 3.3 V and 5 V logic families.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
AD9244–SPECIFICATIONS
DC SPECIFICATIONS
Parameter
RESOLUTION
DC ACCURACY
No Missing Codes
Offset Error
Gain Error
1
Differential Nonlinearity (DNL)
2
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Offset Error
Gain Error (EXT VREF)
1
Gain Error (INT VREF)
3
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (2 VREF)
Load Regulation @ 1 mA
Output Voltage Error (1 VREF)
Load Regulation @ 0.5 mA
Input Resistance
INPUT REFERRED NOISE
VREF = 2 V
VREF = 1 V
ANALOG INPUT
Input Voltage Range (Differential)
VREF = 2 V
VREF = 1 V
Common-Mode Voltage
Input Capacitance
4
Input Bias Current
5
Analog Bandwidth (Full Power)
POWER SUPPLIES
Supply Voltages
AVDD
DRVDD
Supply Current
IAVDD
IDRVDD
PSRR
POWER CONSUMPTION
DC Input
6
Sine Wave Input
2
(AVDD = 5 V, DRVDD = 3 V, f
SAMPLE
= 65 MSPS (–65) or 40 MSPS (–40), Differential Clock Inputs, VREF = 2 V,
External Reference, Differential Analog Inputs, unless otherwise noted.)
Test
Level
VI
VI
VI
VI
VI
V
V
V
V
V
VI
V
IV
V
V
V
V
AD9244BST-65
Min
Typ
Max
14
Guaranteed
±
0.3
±
1.4
±
0.6
±
2.0
±
1.0
±
0.7
±
1.4
±
2.0
±
2.3
±
25
±
29
0.5
±
15
0.25
5
0.8
1.5
0.25
5
0.8
1.5
0.5
±
15
AD9244BST-40
Min
Typ
Max
14
Guaranteed
±
0.3
±
0.6
±
0.6
±
1.3
±
2.0
±
2.3
±
25
±
29
Temp
Full
Full
Full
Full
Full
25°C
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
Unit
Bits
Bits
% FSR
% FSR
LSB
LSB
LSB
ppm/°C
ppm/°C
ppm/°C
mV
mV
mV
mV
kΩ
LSB rms
LSB rms
±
1.4
±
2.0
±
1.0
Full
Full
Full
25°C
25°C
25°C
V
V
V
V
V
V
2
1
0.5
10
500
750
4
0.5
2
1
4
10
500
750
V p-p
V p-p
V
pF
µA
MHz
Full
Full
Full
Full
Full
Full
Full
IV
IV
V
V
V
V
VI
4.75
2.7
5
5.25
5.25
4.75
2.7
5
5.25
5.25
V
V
mA
mA
% FSR
mW
mW
109
12
±
0.05
550
590
64
8
±
0.05
300
345
640
370
NOTES
1
Gain error is based on the ADC only (with a fixed 2.0 V external reference).
2
Measured at maximum clock rate, f
IN
= 2.4 MHz, full-scale sine wave, with approximately 5 pF loading on each output bit.
3
Includes internal voltage reference error.
4
Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 2d for the equivalent analog input structure.
5
Input bias current is due to the inputs looking like a resistor that is dependent on the clock rate.
6
Measured with dc input at maximum clock rate.
Specifications subject to change without notice.
–2–
REV. A
AD9244
AC SPECIFICATIONS (continued)
Parameter
SFDR
f
IN
= 2.4 MHz
f
IN
= 15.5 MHz (–1 dBFS)
f
IN
= 20 MHz
f
IN
= 32.5 MHz
f
IN
= 70 MHz
f
IN
= 100 MHz
f
IN
= 200 MHz
Temp
Full
25°C
Full
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
25°C
Test
Level
VI
I
IV
V
IV
I
IV
I
IV
V
V
V
AD9244BST-65
Min
Typ
Max
78.6
94.5
83
90
81.4
91.8
80.0
86.4
79.5
86.1
86.2
60.7
84.5
56.6
Min
82.5
93.7
AD9244BST-40
Typ
Max
Unit
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
DIGITAL SPECIFICATIONS
Parameter
(AVDD = 5 V, DRVDD = 3 V, VREF = 2 V, External Reference, unless otherwise noted.)
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Test
Level
IV
IV
IV
IV
IV
IV
V
IV
IV
V
IV
IV
V
V
IV
IV
IV
IV
IV
IV
IV
IV
AD9244BST-65
Min
Typ
Max
2
3.5
0.8
3.5
0.8
10
5
0.4
0.25
1.6
2
0.8
5
100
4.5
0.1
2.4
0.4
2.95
0.05
2.8
0.4
2.8
0.4
2.95
0.05
2.4
0.4
4.5
0.1
5
100
2
0.8
0.4
0.25
1.6
5
3.5
0.8
10
AD9244BST-40
Min
Typ
Max
2
3.5
0.8
Unit
V
V
V
V
V
µA
pF
V p-p
V
V
V
V
pF
kΩ
V
V
V
V
V
V
V
V
DIGITAL INPUTS
Logic 1 Voltage (OEB, DRVDD = 3 V)
Logic 1 Voltage (OEB, DRVDD = 5 V)
Logic 0 Voltage (OEB)
Logic 1 Voltage (DFS, DCS)
Logic 0 Voltage (DFS, DCS)
Input Current
Input Capacitance
CLOCK INPUT PARAMETERS
Differential Input Voltage
CLK–Voltage
1
Internal Clock Common-Mode
Single-Ended Input Voltage
Logic 1 Voltage
Logic 0 Voltage
Input Capacitance
Input Resistance
DIGITAL OUTPUTS (DRVDD = 5 V)
2
Logic 1 Voltage (I
OH
= 50
µA)
Logic 0 Voltage (I
OL
= 50
µA)
Logic 1 Voltage (I
OH
= 0.5 mA)
Logic 0 Voltage (I
OL
= 1.6 mA)
DIGITAL OUTPUTS (DRVDD = 3 V)
2
Logic 1 Voltage (I
OH
= 50
µA)
Logic 0 Voltage (I
OL
= 50
µA)
Logic 1 Voltage (I
OH
= 0.5 mA)
Logic 0 Voltage (I
OL
= 1.6 mA)
NOTES
1
See Clock section of Theory of Operation for more details.
2
Output voltage levels measured with 5 pF load on each output.
Specifications subject to change without notice.
–4–
REV. A
Sensor
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