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ACTS04K/Sample

Description
ACT SERIES, HEX 1-INPUT INVERT GATE, CDFP14
Categorysemiconductor    logic   
File Size74KB,3 Pages
ManufacturerIntersil ( Renesas )
Websitehttp://www.intersil.com/cda/home/
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ACTS04K/Sample Overview

ACT SERIES, HEX 1-INPUT INVERT GATE, CDFP14

TM
ACTS04MS
Radiation Hardened
Hex Inverter
Pinouts
14 PIN CERAMIC DUAL-IN-LINE MIL-STD-1835
DESIGNATOR CDIP2-T14, LEAD FINISH C
TOP VIEW
A1 1
Y1 2
A2 3
Y2 4
A3 5
Y3 6
GND 7
14 VCC
13 A6
12 Y6
11 A5
10 Y5
9 A4
8 Y4
January 1996
tle
TS
S)
-
ia-
d-
Features
• Devices QML Qualified in Accordance with MIL-PRF-38535
• Detailed Electrical and Screening Requirements are Contained in
SMD# 5962-96712 and Intersil’s QM Plan
• 1.25 Micron Radiation Hardened SOS CMOS
• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)
• Single Event Upset (SEU) Immunity: <1 x 10
-10
Errors/Bit/Day
(Typ)
• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm
2
/mg
• Dose Rate Upset . . . . . . . . . . . . . . . . >10
11
RAD (Si)/s, 20ns Pulse
• Dose Rate Survivability . . . . . . . . . . . >10
12
RAD (Si)/s, 20ns Pulse
rte
hor
-
ds
r-
ia-
d-
,
• Latch-Up Free Under Any Conditions
• Military Temperature Range . . . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
• Significant Power Reduction Compared to ALSTTL Logic
• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
• Input Logic Levels
- VIL = 0.8V Max
- VIH = VCC/2 Min
• Input Current
1µA at VOL, VOH
• Fast Propagation Delay . . . . . . . . . . . . . . . . . 14ns (Max), 9ns (Typ)
14 PIN CERAMIC FLATPACK MIL-STD-1835
DESIGNATOR CDFP3-F14, LEAD FINISH C
TOP VIEW
A1
Y1
A2
Y2
A3
Y3
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VCC
A6
Y6
A5
Y5
A4
Y4
TRUTH TABLE
Description
The Intersil ACTS04MS is a Radiation Hardened Hex Inverter.
INPUTS
An
L
H
OUTPUTS
Yn
H
L
d,
L,
l-
,
s
ic,
S,
,
rte
The ACTS04MS utilizes advanced CMOS/SOS technology to achieve
high-speed operation. This device is a member of radiation hardened,
high-speed, CMOS/SOS Logic Family.
The ACTS04MS is supplied in a 14 lead Ceramic Flatpack (K suffix) or a
Ceramic Dual-In-Line Package (D suffix).
NOTE: L = Logic Level Low, H = Logic level High
Functional Diagram
An
Yn
Ordering Information
PART NUMBER
5962F9671201VCC
5962F9671201VXC
ACTS04D/Sample
ACTS04K/Sample
ACTS04HMSR
TEMPERATURE RANGE
-55
o
C to +125
o
C
-55
o
C to +125
o
C
25
o
C
25
o
C
25
o
C
SCREENING LEVEL
MIL-PRF-38535 Class V
MIL-PRF-38535 Class V
Sample
Sample
Die
PACKAGE
14 Lead SBDIP
14 Lead Ceramic Flatpack
14 Lead SBDIP
14 Lead Ceramic Flatpack
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil and Design is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2001, All Rights Reserved
1
Spec Number
File Number
518782
3383.1

ACTS04K/Sample Related Products

ACTS04K/Sample ACTS04D/Sample ACTS04HMSR ACTS04MS 5962F9671201VCC 5962F9671201VXC
Description ACT SERIES, HEX 1-INPUT INVERT GATE, CDFP14 ACT SERIES, HEX 1-INPUT INVERT GATE, CDIP14, SIDE BRAZED, CERAMIC, DIP-14 ACT SERIES, HEX 1-INPUT INVERT GATE, UUC16 ACT SERIES, HEX 1-INPUT INVERT GATE, CDIP14 ACT SERIES, HEX 1-INPUT INVERT GATE, CDIP14 ACT SERIES, HEX 1-INPUT INVERT GATE, CDFP14, CERAMIC, DFP-14

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