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UJA1168ATK/FZ

Description
CAN Interface IC UJA1168ATK/HVSON14//F/REEL 13 Q1/T1 *STANDARD MAR
Categorysemiconductor    Analog mixed-signal IC   
File Size1MB,68 Pages
ManufacturerNXP
Websitehttps://www.nxp.com
Environmental Compliance
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UJA1168ATK/FZ Overview

CAN Interface IC UJA1168ATK/HVSON14//F/REEL 13 Q1/T1 *STANDARD MAR

UJA1168ATK/FZ Parametric

Parameter NameAttribute value
Product AttributeAttribute Value
ManufacturerNXP
Product CategoryCAN Interface IC
RoHSDetails
PackagingReel
Factory Pack Quantity6000
UJA1168
Mini high-speed CAN system basis chip for partial networking
Rev. 2 — 16 April 2014
Product data sheet
1. General description
The UJA1168 is a mini high-speed CAN System Basis Chip (SBC) containing an
ISO 11898-2/5/6 compliant HS-CAN transceiver and an integrated 5 V/100 mA supply for
a microcontroller. It also features a watchdog and a Serial Peripheral Interface (SPI). The
UJA1168 can be operated in very low-current Standby and Sleep modes with bus and
local wake-up capability and supports ISO 11898-6 compliant CAN partial networking by
means of a selective wake-up function. The microcontroller supply is switched off in Sleep
mode. The UJA1168TK and UJA1168TK/FD versions contain a battery-related
high-voltage output (INH) for controlling an external voltage regulator, while the
UJA1168TK/VX and UJA1168TK/VX/FD are equipped with a 5 V sensor supply (VEXT).
A dedicated implementation of the partial networking protocol has been embedded into
the UJA1168/FD variants, UJA1168TK/FD and UJA1168TK/VX/FD (see
Section 6.8.1
for
further details on CAN FD). This function is called ‘FD-passive’ and is the ability to ignore
CAN FD frames while waiting for a valid wake-up frame in Sleep/Standby mode. This
additional feature of partial networking is the perfect fit for networks that support both CAN
FD and standard CAN 2.0 communications. It allows normal CAN controllers that do not
need to communicate CAN FD messages to remain in partial networking Sleep/Standby
mode during CAN FD communication without generating bus errors.
The UJA1168 implements the standard CAN physical layer as defined in the current
ISO11898 standard (-2, -5 and -6). Pending the release of the updated version of
ISO11898 including CAN FD, additional timing parameters defining loop delay symmetry
are included. This implementation enables reliable communication in the CAN FD fast
phase at data rates up to 2 Mbit/s.
A number of configuration settings are stored in non-volatile memory, allowing the SBC to
be adapted for use in a specific application. This makes it possible to configure the
power-on behavior of the UJA1168 to meet the requirements of different applications.
2. Features and benefits
2.1 General
ISO 11898-2, ISO 11898-5 and ISO 11898-6 compliant high-speed CAN transceiver
Loop delay symmetry timing enables reliable communication at data rates up to
2 Mbit/s in the CAN FD fast phase
Autonomous bus biasing according to ISO 11898-6
Fully integrated 5 V/100 mA low-drop voltage regulator for 5 V microcontroller
supply (V1)
Bus connections are truly floating when power to pin BAT is off

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