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5AGXBB7D4F40C5N

Description
FPGA - Field Programmable Gate Array FPGA - Arria V GX 19024 LABs 704 IOs
Categorysemiconductor    Programmable logic devices   
File Size875KB,40 Pages
ManufacturerIntel
Websitehttp://www.intel.com/
Environmental Compliance
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FPGA - Field Programmable Gate Array FPGA - Arria V GX 19024 LABs 704 IOs

5AGXBB7D4F40C5N Parametric

Parameter NameAttribute value
Product AttributeAttribute Value
ManufacturerIntel
Product CategoryFPGA - Field Programmable Gate Array
Shipping RestrictionsThis product may require additional documentation to export from the United States.
RoHSDetails
ProductArria V GX
Number of Logic Elements504000
Number of Logic Array Blocks - LABs19024
Number of I/Os704 I/O
Operating Supply Voltage850 mV, 1.1 V, 1.15 V
Minimum Operating Temperature0 C
Maximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT
Package / CaseFBGA-1517
PackagingTray
Data Rate6.5536 Gb/s
Embedded Block RAM - EBR2906 kbit
Maximum Operating Frequency800 MHz
Moisture SensitiveYes
Number of Transceivers9 Transceiver
Factory Pack Quantity21
Total Memory27046 kbit
2015.12.21
Arria V Device Overview
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AV-51001
The Arria
®
V device family consists of the most comprehensive offerings of mid-range FPGAs ranging
from the lowest power for 6 gigabits per second (Gbps) and 10 Gbps applications, to the highest mid-
range FPGA bandwidth 12.5 Gbps transceivers.
The Arria V devices are ideal for power-sensitive wireless infrastructure equipment, 20G/40G bridging,
switching, and packet processing applications, high-definition video processing and image manipulation,
and intensive digital signal processing (DSP) applications.
Arria V Device Handbook: Known Issues
Lists the planned updates to the Arria V Device Handbook chapters.
Related Information
Key Advantages of Arria V Devices
Table 1: Key Advantages of the Arria V Device Family
Advantage
Supporting Feature
Lowest static power in its
class
• Built on TSMC's 28 nm process technology and includes an abundance of
hard intellectual property (IP) blocks
• Power-optimized MultiTrack routing and core architecture
• Up to 50% lower power consumption than the previous generation
device
• Lowest power transceivers of any midrange family
Improved logic integration • 8-input adaptive logic module (ALM)
and differentiation capabil‐ • Up to 38.38 megabits (Mb) of embedded memory
ities
• Variable-precision digital signal processing (DSP) blocks
Increased bandwidth
capacity
Hard processor system
(HPS) with integrated
ARM
®
Cortex
-A9
MPCore processor
• Serial data rates up to 12.5 Gbps
• Hard memory controllers
• Tight integration of a dual-core ARM Cortex-A9 MPCore processor,
hard IP, and an FPGA in a single Arria V system-on-a-chip (SoC)
• Supports over 128 Gbps peak bandwidth with integrated data coherency
between the processor and the FPGA fabric
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at
www.altera.com/common/legal.html.
Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
©
ISO
9001:2008
Registered
www.altera.com
101 Innovation Drive, San Jose, CA 95134
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