Features
•
Integrated PLL Loop Filter
•
ESD Protection also at ANT1/ANT2
•
•
•
•
•
•
•
•
•
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(4 kV HBM/200 V MM; Except Pin 2: 4 kV HBM/100 V MM)
High Output Power (5.5 dBm) with Low Supply Current (8.5 mA)
Modulation Scheme ASK/FSK
– FSK Modulation is Achieved by Connecting an Additional Capacitor Between the
XTAL Load Capacitor and the Open Drain Output of the Modulating Microcontroller
Easy to Design-in Due to Excellent Isolation of the PLL from the PA and Power Supply
Single Li-cell for Power Supply
Supply Voltage 2.0 V to 4.0 V in the Temperature Range of -40° C to 85° C/125° C
Package TSSOP8L
Single-ended Antenna Output with High Efficient Power Amplifier
CLK Output for Clocking the Microcontroller
One-chip Solution with Minimum External Circuitry
125° C Operation for Tire Pressure Systems
UHF ASK/FSK
Transmitter
T5750
Description
The T5750 is a PLL transmitter IC which has been developed for the demands of RF
low-cost transmission systems at data rates up to 32 kBaud. The transmitting
frequency range is 868 MHz to 928 MHz. It can be used in both FSK and ASK
systems.
Preliminary
Figure 1.
System Block Diagram
UHF ASK/FSK
Remote control transmitter
UHF ASK/FSK
Remote control receiver
1 Li cell
T5750
T5760/
T5761
PLL
Demod.
Control
1...3
µC
Keys
Encoder
M44Cx9x
XTO
IF Amp
Antenna Antenna
VCO
PLL
XTO
Power
amp.
LNA
VCO
Rev. 4546B–RKE–07/04
Pin Configuration
Figure 2.
Pinning TSSOP8L
CLK
1
8
ENABLE
GND
PA_ENABLE
2
T5750
7
ANT2
3
6
VS
ANT1
4
5
XTAL
Pin Description
Pin
Symbol
Function
Configuration
VS
1
CLK
Clock output signal for micro con roller
The clock output frequency is set by the
crystal to f
XTAL
/4
100
100
CLK
PA_ENABLE
50k
Uref=1.1V
2
PA_ENABLE
Switches on power amplifier, used for
ASK modulation
20 µA
ANT1
3
4
ANT2
ANT1
Emitter of antenna output stage
Open collector antenna output
ANT2
VS
1.5k
1.2k
VS
5
XTAL
Connection for crystal
XTAL
182 mA
6
7
8
VS
GND
ENABLE
Supply voltage
Ground
Enable input
See ESD protection circuitry (see Figure 8 on page 8)
See ESD protection circuitry (see Figure 8 on page 8)
ENABLE
200k
2
T5750 [Preliminary]
4546B–RKE–07/04
T5750 [Preliminary]
Figure 3.
Block Diagram
T5750
Power up / down
CLK
1
f
4
f
64
ENABLE
8
PA_ENABLE
GND
2
PFD
7
CP
ANT2
VS
3
LF
6
ANT1
XTAL
PA
4
VCO
XTO
5
PLL
General Description
This fully integrated PLL transmitter allows particularly simple, low-cost RF miniature
transmitters to be assembled. The VCO is locked to 64
×
f
XTAL
hence a 13.5672 MHz
crystal is needed for a 868.3 MHz transmitter and a 14.2969 MHz crystal for a 915 MHz
transmitter. All other PLL and VCO peripheral elements are integrated.
The XTO is a series resonance oscillator so that only one capacitor together with a
crystal connected in series to GND are needed as external elements.
The crystal oscillator together with the PLL needs typically <1 ms until the PLL is locked
and the CLK output is stable. There is a wait time of
≥
4 ms must be used until the CLK
is used for the microcontroller and the PA is switched on.
The power amplifier is an open-collector output delivering a current pulse which is nearly
independent from the load impedance. The delivered output power is hence controllable
via the connected load impedance.
This output configuration enables a simple matching to any kind of antenna or to 50
Ω.
A
high power efficiency of
η=
P
out
/(I
S,PA
×
V
S
) of 24% for the power amplifier at 868.3 MHz
results when an optimized load impedance of Z
Load
= (166 + j226)
Ω
is used at 3 V sup-
ply voltage.
3
4546B–RKE–07/04
Functional
Description
If ENABLE = L and the PA_ENABLE = L, the circuit is in standby mode consuming only
a very small amount of current, so that a lithium cell used as power supply can work for
several years.
With ENABLE = H the XTO, PLL and the CLK driver are switched on. If PA_ENABLE
remains L only the PLL and the XTO is running and the CLK signal is delivered to the
microcontroller. The VCO locks to 64 times the XTO frequency.
With ENABLE = H and PA_ENABLE = H the PLL, XTO, CLK driver and the power
amplifier are on. With PA_ENABLE the power amplifier can be switched on and off,
which is used to perform the ASK modulation.
ASK Transmission
The T5750 is activated by ENABLE = H. PA_ENABLE must remain L for t
≥
4 ms, then
the CLK signal can be taken to clock the microcontroller and the output power can be
modulated by means of Pin PA_ENABLE. After transmission PA_ENABLE is switched
to L and the microcontroller switches back to internal clocking. The T5750 is switched
back to standby mode with ENABLE = L.
The T5750 is activated by ENABLE = H. PA_ENABLE must remain L for t
≥
4 ms, then
the CLK signal can be taken to clock the microcontroller and the power amplifier is
switched on with PA_ENABLE = H. The chip is then ready for FSK modulation. The
microcontroller starts to switch on and off the capacitor between the XTAL load capaci-
tor and GND with an open-drain output port, thus changing the reference frequency of
the PLL. If the switch is closed, the output frequency is lower than if the switch is open.
After transmission PA_ENABLE is switched to L and the microcontroller switches back
to internal clocking. The T5750 is switched back to standby mode with ENABLE = L.
The accuracy of the frequency deviation with XTAL pulling method is about
±25%
when
the following tolerances are considered.
Figure 4.
Tolerances of Frequency Modulation
FSK Transmission
~
V
S
C
Stray1
XTAL
C
Stray2
C
M
L
M
C
0
Crystal equivalent circuit
R
S
C
4
C
5
C
Switch
Using C
4
= 9.2 pF ±2%, C
5
= 6.8 pF ±5%, a switch port with C
Switch
= 3 pF ±10%, stray
capacitances on each side of the crystal of C
Stray1
= C
Stray2
= 1 pF ±10%, a parallel
capacitance of the crystal of C
0
= 3.2 pF ±10% and a crystal with C
M
= 13 fF ±10%, an
FSK deviation of ±21.5 kHz typical with worst case tolerances of ±16.8 kHz to
±28.0 kHz results.
~
CLK Output
Clock Pulse Take-over
An output CLK signal is provided for a connected microcontroller, the delivered signal is
CMOS compatible if the load capacitance is lower than 10 pF.
The clock of the crystal oscillator can be used for clocking the microcontroller. Atmel’s
M4xCx9x has the special feature of starting with an integrated RC-oscillator to switch on
the T5750 with ENABLE = H, and after 4 ms to assume the clock signal of the transmis-
sion IC, so that the message can be sent with crystal accuracy.
4
T5750 [Preliminary]
4546B–RKE–07/04
T5750 [Preliminary]
Output Matching and Power
Setting
The output power is set by the load impedance of the antenna. The maximum output
power is achieved with a load impedance of Z
Load,opt
= (166 + j226)
Ω
at 868.3 MHz.
There must be a low resistive path to V
S
to deliver the DC current.
The delivered current pulse of the power amplifier is 7.7 mA and the maximum output
power is delivered to a resistive load of 475
Ω
if the 0.53 pF output capacitance of the
power amplifier is compensated by the load impedance.
An optimum load impedance of:
Z
Load
= 475
Ω
|| j/(2
× π ×
f
×
0.53 pF) = (166 + j226)
Ω
thus results for the maximum out-
put power of 5.5 dBm.
The load impedance is defined as the impedance seen from the T5750’s ANT1, ANT2
into the matching network. Do not confuse this large signal load impedance with a small
signal input impedance delivered as input characteristic of RF amplifiers and measured
from the application into the IC instead of from the IC into the application for a power
amplifier.
Less output power is achieved by lowering the real parallel part of 475
Ω
where the
parallel imaginary part should be kept constant.
Output power measurement can be done with the circuit of Figure 5. Note that the com-
ponent values must be changed to compensate the individual board parasitics until the
T5750 has the right load impedance Z
Load,opt
= (166 + j226)
Ω
at 868.3 MHz. Also the
damping of the cable used to measure the output power must be calibrated out.
Figure 5.
Output Power Measurement
V
S
C
1
= 1n
L
1
= 10n
Power
meter
Z = 50
Ω
Z
Lopt
ANT2
~
C
2
= 1.5p
C
3
= 2.7p
Rin
50
Ω
ANT1
Application Circuit
For the supply-voltage blocking capacitor C
3
a value of 68 nF/X7R is recommended
(see Figure 6 on page 6 and Figure 7 on page 7). C
1
and C
2
are used to match the loop
antenna to the power amplifier where C
1
typically is 3.9 pF/NP0 and C
2
is 1 pF/NP0; for
C
2
two capacitors in series should be used to achieve a better tolerance value and to
have the possibility to realize the Z
Load,opt
by using standard valued capacitors.
C
1
forms together with the pins of T5750 and the PCB board wires a series resonance
loop that suppresses the 1
st
harmonic, hence the position of C
1
on the PCB is important.
Normally the best suppression is achieved when C
1
is placed as close as possible to the
Pins ANT1 and ANT2.
The loop antenna should not exceed a width of 1.5 mm, otherwise the Q-factor of the
loop antenna is too high.
L
1
(≈ 50 nH to 100 nH) can be printed on PCB. C
4
should be selected so that the XTO
runs on the load resonance frequency of the crystal. Normally, a value of 12 pF results
for a 15 pF load-capacitance crystal.
~
5
4546B–RKE–07/04
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