response authentication functionality with an imple-
mentation based on the FIPS 180-3-specified Secure
Hash Algorithm (SHA-256). A 512-bit user-program-
mable EEPROM array provides nonvolatile storage of
application data. Additional protected memory holds a
read-protected secret for SHA-256 operations and set-
tings for memory protection control. Each device has
its own guaranteed unique 64-bit ROM identification
number (ROM ID) that is factory programmed into the
chip. This unique ROM ID is used as a fundamental input
parameter for cryptographic operations and also serves
as an electronic serial number within the application. A
bidirectional security model enables two-way authen-
tication between a host system and slave-embedded
DS28E15. Slave-to-host authentication is used by a host
system to securely validate that an attached or embed-
ded DS28E15 is authentic. Host-to-slave authentication is
used to protect DS28E15 user memory from being modi-
fied by a unauthentic host. The DS28E15 communicates
over the single-contact 1-Wire
M
bus at overdrive speed.
The communication follows the 1-Wire protocol with the
ROM ID acting as node address in the case of a multi-
device 1-Wire network.
Benefits and Features
●
512-Bit EEPROM with SHA-256 Authentication for
Reads and Writes
• Symmetric-Key-Based Bidirectional Secure
Authentication Model Based on SHA-256
• Strong Authentication with a High-Bit-Count User
Programmable Secret and Input Challenge
• 512 Bits of User EEPROM Partitioned Into Two
Pages of 256 Bits
• User-Programmable and Irreversible EEPROM
Protection Modes Including Authentication, Write
and Read Protect, and OTP/EPROM Emulation
•
Unique Factory-Programmed, 64-Bit Identification
Number
●
Minimalist 1-Wire Interface Lowers Cost and
Interface Complexity
• Reduces Control, Address, Data, Power, and
Programming Signals to a Single Data Pin
• ±8kV HBM ESD Protection (typ)
• 2-Pin SFN, 6-Pin TDFN-EP, and 6-Pin TSOC
Packages
• Operating Range: 3.3V ±10%, -40°C to +85°C
Typical Application Circuit
R
P
= 1.1kΩ
MAXIMUM I
2
C BUS CAPACITANCE 320pF
3.3V
R
P
(I
2
C PORT)
µC
SLPZ
SDA
SCL
V
CC
Applications
Authentication of Consumables
Secure Feature Control
DS2465
IO
1-Wire LINE
Ordering Information
appears at end of data sheet.
DS28E15
DeepCover is a trademark and 1-Wire is a registered trademark of Maxim Integrated Products, Inc.
219-0018; Rev 3; 3/15
ABRIDGED DATA SHEET
DS28E15
DeepCover Secure Authenticator with
1-Wire SHA-256 and 512-Bit User EEPROM
Absolute Maximum Ratings
IO Voltage Range to GND....................................-0.5V to +4.0V
IO Sink Current ...................................................................20mA
Operating Temperature Range .......................... -40NC to +85NC
Junction Temperature .....................................................+150NC
Storage Temperature Range............................ -55NC to +125NC
Lead Temperature (TDFN, TSOC only; soldering, 10s)..+300NC
Soldering Temperature (TDFN, TSOC only; reflow) ........+260NC
Note:
The SFN package is qualified for electro-mechanical contact applications only, not for soldering. For more information, refer
to
Application Note 4132:
Attachment Methods for the Electro-Mechanical SFN Package.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Electrical Characteristics
(T
A
= -40NC to +85NC, unless otherwise noted.) (Note 1)
PARAMETER
IO PIN: GENERAL DATA
1-Wire Pullup Voltage
1-Wire Pullup Resistance
Input Capacitance
Input Load Current
High-to-Low Switching Threshold
Input Low Voltage
Low-to-High Switching Threshold
Switching Hysteresis
Output Low Voltage
Recovery Time
Time Slot Duration
Reset Low Time
Reset High Time
Presence-Detect Sample Time
IO PIN: 1-Wire WRITE
Write-Zero Low Time
Write-One Low Time
IO PIN: 1-Wire READ
Read Low Time
Read Sample Time
t
RL
t
MSR
(Notes 2, 17)
(Notes 2, 17)
1
t
RL
+
d
2-
d
2
Fs
Fs
t
W0L
t
W1L
(Notes 2, 16)
(Notes 2, 16)
8
1
16
2
Fs
Fs
V
PUP
R
PUP
C
IO
I
L
V
TL
V
IL
V
TH
V
HY
V
OL
t
REC
t
SLOT
t
RSTL
t
RSTH
t
MSP
(Note 2)
V
PUP
= 3.3V
Q10%
(Note 3)
(Notes 4, 5)
IO pin at V
PUP
(Notes 6, 7)
(Notes 2, 8)
(Notes 6, 9)
(Notes 6, 10)
I
OL
= 4mA (Note 11)
R
PUP
= 1500I (Notes 2, 12)
(Notes 2, 13)
(Note 2)
(Note 14)
(Notes 2, 15)
5
13
48
48
8
10
80
0.75 x
V
PUP
0.3
0.4
2.97
300
1500
5
0.65 x
V
PUP
0.3
19.5
3.63
1500
V
I
pF
FA
V
V
V
V
V
Fs
Fs
Fs
Fs
Fs
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
IO PIN: 1-Wire RESET, PRESENCE-DETECT CYCLE
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Maxim Integrated
│
2
ABRIDGED DATA SHEET
DS28E15
DeepCover Secure Authenticator with
1-Wire SHA-256 and 512-Bit User EEPROM
Electrical Characteristics (continued)
(T
A
= -40NC to +85NC, unless otherwise noted.) (Note 1)
PARAMETER
EEPROM
Programming Current
Programming Time for a 32-Bit
Segment or Page Protection
Programming Time for the Secret
Write/Erase Cycling Endurance
Data Retention
SHA-256 ENGINE
Computation Current
Computation Time
I
CSHA
t
CSHA
Refer to the full data sheet.
mA
ms
I
PROG
t
PRD
t
PRS
N
CY
t
DR
T
A
= +85NC (Notes 21, 22)
T
A
= +85NC (Notes 23, 24, 25)
100k
10
V
PUP
= 3.63V (Notes 5, 18)
Refer to the full data sheet.
1
mA
ms
ms
—
Years
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Note 1:
Limits are 100% production tested at T
A
= +25°C and/or T
A
= +85°C. Limits over the operating temperature range and
relevant supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed.
Note 2:
System requirement.
Note 3:
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery
times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times.
Note 4:
Typical value represents the internal parasite capacitance when V
PUP
is first applied. Once the parasite capacitance is
charged, it does not affect normal communication.
Note 5:
Guaranteed by design and/or characterization only. Not production tested.
Note 6:
V
TL
, V
TH
, and V
HY
are a function of the internal supply voltage, which is a function of V
PUP
, R
PUP
, 1-Wire timing, and
capacitive loading on IO. Lower V
PUP
, higher R
PUP
, shorter t
REC
, and heavier capacitive loading all lead to lower values
of V
TL
, V
TH
, and V
HY
.
Note 7:
Voltage below which, during a falling edge on IO, a logic 0 is detected.
Note 8:
The voltage on IO must be less than or equal to V
IL(MAX)
at all times the master is driving IO to a logic 0 level.
Note 9:
Voltage above which, during a rising edge on IO, a logic 1 is detected.
Note 10:
After V
TH
is crossed during a rising edge on IO, the voltage on IO must drop by at least V
HY
to be detected as logic 0.
Note 11:
The I-V characteristic is linear for voltages less than 1V.
Note 12:
Applies to a single device attached to a 1-Wire line.
Note 13:
Defines maximum possible bit rate. Equal to 1/(t
W0L(MIN)
+ t
REC(MIN)
).
Note 14:
An additional reset or communication sequence cannot begin until the reset high time has expired.
Note 15:
Interval after t
RSTL
during which a bus master can read a logic 0 on IO if there is a DS28E15 present. The power-up pres-
ence detect pulse could be outside this interval but will be complete within 2ms after power-up.
Note 16: ε
in
Figure 11
represents the time required for the pullup circuitry to pull the voltage on IO up from V
IL
to V
TH
. The actual
maximum duration for the master to pull the line low is t
W1L(MAX)
+ t
F
-
ε
and t
W0L(MAX)
+ t
F
-
ε,
respectively.
Note 17:
d
in
Figure 11
represents the time required for the pullup circuitry to pull the voltage on IO up from V
IL
to the input-high
threshold of the bus master. The actual maximum duration for the master to pull the line low is t
RL(MAX)
+ t
F
.
Note 18:
Current drawn from IO during the EEPROM programming interval or SHA-256 computation. The pullup circuit on IO during
the programming interval and SHA-256 computation should be such that the voltage at IO is greater than or equal to 2.0V.
Note 19: Refer to the full data sheet.
Note 20: Refer to the full data sheet.
Note 21:
Write-cycle endurance is tested in compliance with JESD47G.
Note 22:
Not 100% production tested; guaranteed by reliability monitor sampling.
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Maxim Integrated
│
3
ABRIDGED DATA SHEET
DS28E15
DeepCover Secure Authenticator with
1-Wire SHA-256 and 512-Bit User EEPROM
Electrical Characteristics (continued)
(T
A
= -40NC to +85NC, unless otherwise noted.) (Note 1)
Note 23:
Data retention is tested in compliance with JESD47G.
Note 24:
Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to the-
data sheet limit at operating temperature range is established by reliability testing.
Note 25:
EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-term storage at elevated tem-
peratures is not recommended.
Note 26: Refer to the full data sheet.
Pin Configurations
TOP VIEW
TOP VIEW
DS28E15
N.C.
IO
GND
1
2
3
BOTTOM VIEW
6
N.C.
N.C.
N.C.
+
GND
IO
N.C.
1
2
3
DS28E15
6 N.C.
5
4
N.C.
N.C.
+
28E15
ymrrF
*EP
GND
DS28E15
IO
2
5
4
1
TSOC
TDFN-EP
(3mm × 3mm)
SFN
(3.5mm
×
6.5mm
×
0.75mm)
NOTE:
THE SFN PACKAGE IS QUALIFIED FOR ELECTRO-
MECHANICAL CONTACT APPLICATIONS ONLY, NOT FOR
SOLDERING. FOR MORE INFORMATION, REFER TO
APPLICATION NOTE 4132:
ATTACHMENT METHODS FOR
THE ELECTRO-MECHANICAL SFN PACKAGE.
*EXPOSED PAD
Pin Descriptions
PIN
SFN
—
1
2
—
TDFN-EP
1, 4, 5, 6
2
3
—
TSOC
3– 6
2
1
—
NAME
N.C.
IO
GND
EP
Not Connected
1-Wire Bus Interface. Open-drain signal that requires an external pullup resistor.
Ground Reference
Exposed Pad (TDFN Only). Solder evenly to the board’s ground plane for proper
operation. Refer to Application Note 3273:
Exposed Pads: A Brief Introduction
for
additional information.
FUNCTION
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Maxim Integrated
│
4
DS28E15
DeepCover Secure Authenticator with
1-Wire SHA-256 and 512-Bit User EEPROM
Note to readers:
This document is an abridged version of the full data sheet. Additional device infor-
mation is available only in the full version of the data sheet. To request the full data sheet, go to
www.maximintegrated.com/DS28E15
and click on
Request Full Data Sheet.
Ordering Information
PART
DS28E15G+
DS28E15G+T
DS28E15Q+T
DS28E15P+
DS28E15P+T
TEMP RANGE
-40NC to +85NC
-40NC to +85NC
-40NC to +85NC
-40NC to +85NC
-40NC to +85NC
PIN-PACKAGE
2 SFN
2 SFN (2.5k pcs)
6 TDFN-EP*
(2.5k pcs)
6 TSOC
6 TSOC (4k pcs)
Package Information
For the latest package outline information and land patterns (foot-
prints), go to
www.maximintegrated.com/packages.
Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
2 SFN
6 TDFN-EP
6 TSOC
PACKAGE
CODE
T23A6N+1
T633+2
D6+1
OUTLINE
NO.
21-0575
21-0137
21-0382
LAND
PATTERN NO.
—
90-0058
90-0321
+Denotes
a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
*EP = Exposed pad.
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed.
Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
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