NB7L111M
2.5V/3.3V, 6.125Gb/s 2:1:10
Differential Clock/Data
Driver with CML Output
Description
The NB7L111M is a low skew 2:1:10 differential clock/data driver,
designed with clock/data distribution in mind. It accepts two
clock/data sources into multiplexer input and reproduces ten identical
CML differential outputs. This device is ideal for clock/data
distribution across the backplane or a board, and redundant clock
switchover applications.
The input signals can be either differential or single–ended (if the
external reference voltage is provided). Differential inputs incorporate
internal 50
W
termination resistors and accept Negative ECL (NECL),
Positive ECL (PECL), LVCMOS, LVTTL, CML, or LVDS (using
appropriate power supplies). The differential 16 mA CML output
provides matching internal 50
W
termination, and 400 mV output
swing when externally terminated 50
W
to V
CC.
The NB7L111M operates from a 2.5 V
$5%
supply or a
3.3 V
$5%
supply and is guaranteed over the full industrial
temperature range of −40°C to +85°C. This device is packaged in a
low profile 8x8 mm, QFN−52 package with 0.5 mm pitch (see
package dimension on the back of the datasheet).
Application notes, models, and support documentation are available
at
www.onsemi.com.
Features
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1
52
QFN−52
MN SUFFIX
CASE 485M
MARKING DIAGRAM*
52
1
NB7L
111M
AWLYYWWG
•
•
•
•
•
•
•
•
•
•
•
•
•
Maximum Input Clock Frequency > 5.5 GHz Typical
Maximum Input Data Rate > 6.125 Gb/s Typical
< 0.5 ps Maximum Clock RMS Jitter
< 15 ps Maximum Data Dependent Jitter at 3.125 Gb/s
50 ps Typical Rise and Fall Times
240 ps Typical Propagation Delay
2 ps Typical Duty Cycle Skew
10 ps Typical Within Device Skew
15 ps Typical Device−to−Device Skew
Operating Range: V
CC
= 2.5 V
$5
and 3.3 V
$5
400 mV Differential CML Output Swing
50
W
Internal Input and Output Termination Resistors
These Devices are Pb−Free and are RoHS Compliant*
A
WL
YY
WW
G
= Assembly Site
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information on page 12 of
this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2015
1
April, 2015 − Rev. 7
Publication Order Number:
NB7L111M/D
NB7L111M
V
CC
V
CC
V
EE
V
EE
V
EE
40
39
38
37
36
35
34
NC
NC
41
Q0
Q0
Q1
Q1
Q2
44
Q2
43
Exposed Pad (EP)
52
51
50
49
48
47
46
45
V
EE
VTCLK0
CLK0
CLK0
VTCLK0
VTSEL
SEL
SEL
VTSEL
VTCLK1
CLK1
CLK1
VTCLK1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
42
V
CC
Q3
Q3
V
EE
Q4
Q4
V
EE
Q5
Q5
V
EE
Q6
Q6
V
CC
QFN52
33
32
31
30
29
28
27
Q9
Q9
Q8
Q8
V
EE
V
EE
Q7
Q7
V
CC
V
CC
Figure 1. Pinout
(Top View)
Q
0
V
CC
V
EE
Q
0
Q
1
Q
1
Q
2
VTCLK0
50
W
CLK0
0
CLK0
50
W
VTCLK0
VTCLK1
50
W
CLK1
1
CLK1
50
W
VTCLK1
VTSEL
50
W
SEL
SEL
50
W
VTSEL
R
2
R
3
Q
2
Q
3
Q
3
Q
4
Q
4
Q
5
Q
5
Q
6
Q
6
Q
7
Q
7
R
1
Q
8
Q
8
Q
9
Q
9
Figure 2. Logic Diagram
Table 1. FUNCTION TABLE
SEL
LOW
HIGH
SEL
HIGH
LOW
CLK0/CLK0
ON
OFF
CLK1/CLK1
OFF
ON
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2
V
EE
NC
NC
NB7L111M
Table 2. PIN DESCRIPTION
Pin
15, 24, 27, 39, 42, 51
1, 18, 21, 26, 30, 33,
36, 40, 45, 48
2
3
Name
V
CC
V
EE
VTCLK0
CLK0
I/O
−
−
−
LVPECL, CML,
LVCMOS, LVTTL,
LVDS Input
LVPECL, CML,
LVCMOS, LVTTL,
LVDS Input
−
Description
Positive supply voltage. All V
CC
pins must be externally connected to
power supply to guarantee proper operation.
Negative supply voltage. All V
EE
pins must be externally connected to
power supply to guarantee proper operation.
Internal 50
W
termination pin for CLK0. (Note 2)
Non−inverted differential clock/data input 0 (Note 2).
4
CLK0
Inverted differential clock/data input 0 (Note 2).
5
6
7
VTCLK0
VTSEL
SEL
Internal 50
W
termination pin for CLK0. (Note 2)
Internal 50
W
termination pin for SEL. (Note 2)
LVPECL, CML,
LVCMOS, LVTTL,
LVDS Input
LVPECL, CML,
LVCMOS, LVTTL,
LVDS Input
LVPECL, CML,
LVCMOS, LVTTL,
LVDS Input
−
LVPECL, CML,
LVCMOS, LVTTL,
LVDS Input
LVPECL, CML,
LVCMOS, LVTTL,
LVDS Input
−
−
CML Outputs
CML Outputs
−
Non−inverted differential clock/data select input. Internal 75 kW to V
EE
.
8
SEL
Inverted differential clock/data select input. Internal 56 KW to V
CC
and
56 kW to V
EE
bias this pin to (V
CC
−V
EE
)/2.
Internal 50
W
termination pin for SEL. (Note 2)
9
VTSEL
10
11
VTCLK1
CLK1
Internal 50
W
termination pin for CLK1. (Note 2)
Non−inverted differential clock/data input 1 (Note 2).
12
CLK1
Inverted differential clock/data input 1 (Note 2).
13
14, 25, 41, 52
17, 20, 23, 29, 32, 35,
38, 44, 47, 50
16, 19, 22, 28, 31, 34,
37, 43, 46, 49
EP
VTCLK1
NC
Q[0−9]
Q[0−9]
−
Internal 50
W
termination pin for CLK1. (Note 2)
Non−inverted CML outputs [0−9] with internal 50
W
source termination
resistor (Note 1).
Inverted CML outputs [0−9] with internal 50
W
source termination
resistor (Note 1).
Exposed Pad (EP). The thermally exposed pad on package bottom (see
case drawing) must be attached to a heat−sinking conduit on the printed
circuit board.
1. CML output requires 50
W
receiver termination resistor to V
CC
for proper operation.
2. In the differential configuration when the input termination pin (VTCLK, VTCLK) are connected to a common termination voltage or left open,
and if no signal is applied on CLK and CLK then the device will be susceptible to self−oscillation.
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3
NB7L111M
Table 3. ATTRIBUTES
Characteristics
Input Default State Resistors
ESD Protection
Moisture Sensitivity (Note 3)
QFN−52
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
3. For additional information, see Application Note AND8003/D.
Oxygen Index: 28 to 34
R1, R3
R2
Human Body Model
Machine Model
Pb Pkg
Level 2
Value
56 kW
75 kW
> 1400 V
> 80 V
Pb−Free Pkg
Level 1
UL 94 V−0 @ 0.125 in
339
Table 4. MAXIMUM RATINGS
(Note 4)
Symbol
V
CC
V
I
V
INPP
I
in
I
out
T
A
T
stg
q
JA
q
JC
T
sol
Parameter
Positive Power Supply
Input Voltage
Differential Input Voltage |CLK − CLK|
Input Current Through R
T
(50
W
Resistor)
Output Current
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
(Note 5)
Thermal Resistance (Junction−to−Case)
Wave Solder
Pb
Pb−Free
0 lfpm
500 lfpm
1S2P (Note 8)
QFN52
QFN52
Condition 1
V
EE
= 0 V
V
EE
= 0 V
V
CC
− V
EE
≥
2.8 V
V
CC
− V
EE
< 2.8 V
Continuous
Surge
Continuous
Surge
QFN52
V
EE
v
V
I
v
V
CC
Condition 2
Rating
3.6
3.6
2.8
|V
CC
− V
EE
|
25
50
25
50
−40 to +85
−65 to +150
25
19.6
21
265
265
Unit
V
V
V
V
mA
mA
mA
mA
°C
°C
°C/W
°C/W
°C/W
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
4. Maximum Ratings are those values beyond which device damage may occur.
5. JEDEC standard multilayer board − 1S2P (1 signal, 2 power).
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4
NB7L111M
Table 5. DC CHARACTERISTICS
V
CC
= 2.375 V 2.625 V and 3.135 V to 3.465 V, V
EE
= 0 V, T
A
= −40°C to +85°C (Notes 6 and 7)
Symbol
I
CC
Characteristic
Power Supply Current (Inputs and Outputs Open)
V
CC
= 2.375 V to 2.625 V
V
CC
= 3.135 V to 3.465 V
Output HIGH Voltage (Notes 6 and 7)
Output LOW Voltage (Notes 6 and 7)
V
CC
= 2.375 V to 2.625 V
V
CC
= 3.135 V to 3.465 V
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED
(See Figures 13 and 15)
V
th
V
IH
V
IL
Input Threshold Reference Voltage Range (Note 8)
Single−ended Input HIGH Voltage (Note 7)
Single−ended Input LOW Voltage (Note 7)
1125
V
th
+ 75
V
EE
V
CC
– 75
V
CC
V
CC
– 150
mV
mV
mV
V
CC
− 440
V
CC
− 490
V
CC
− 350
V
CC
− 400
V
CC
– 290
V
CC
− 340
Min
255
270
V
CC
− 40
Typ
290
305
V
CC
− 20
Max
325
340
V
CC
mV
mV
Unit
mA
V
OH
V
OL
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY
(See Figures 14 and 16)
V
IHD
V
ILD
V
CMR
V
ID
I
IH
I
IL
R
TIN
R
TOUT
R
Temp
Coef
Differential Input HIGH Voltage
Differential Input LOW Voltage
Input Common Mode Range (Differential Configuration) (Note 9)
Differential Input Voltage (V
IHD
− V
ILD
)
Input HIGH Current
(Termination Pins Open)
Input LOW Current
(Termination Pins Open)
Internal Input Termination Resistor
Internal Output Termination Resistor
Internal I/O Termination Resistor Temperature Coefficient
CLK[0−1]/CLK[0−1]
SEL/SEL
CLK[0−1]/CLK[0−1]
SEL/SEL
1200
V
EE
1163
75
−100
−150
−100
−150
45
45
5
5
50
50
−3.75
V
CC
V
CC
– 75
V
CC
– 37
2500
100
150
100
150
55
55
mV
mV
mV
mV
mA
mA
W
W
mW/C
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
6. CML outputs require 50
W
receiver termination resistors to V
CC
for proper operation.
7. Input and output parameters vary 1:1 with V
CC
.
8. V
th
is applied to the complementary input when operating in single−ended mode.
9. V
CMR
(MIN) varies 1:1 with V
EE
, V
CMR
(MAX) varies 1:1 with V
CC
.
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