Twos complement temperature value of sign bit plus
12 ADC bits (power-up default resolution)
Twos complement temperature value of sign bit plus
15 ADC bits (Bit 7 = 1 in the configuration register)
13-bit resolution (sign + 12 bits)
16-bit resolution (sign + 15 bits)
Continuous conversion and one-shot conversion mode
First conversion on power-up only
Conversion time for 1 SPS mode
Temperature cycle = 25°C to 125°C and back to 25°C
T
A
= 25°C
T
A
= 25°C
Temperature Resolution
13-Bit
16-Bit
Temperature Conversion Time
Fast Temperature Conversion Time
1 SPS Conversion Time
Temperature Hysteresis
Repeatability
DC PSRR
DIGITAL OUTPUTS (CT, INT), OPEN
DRAIN
High Output Leakage Current, I
OH
Output Low Voltage, V
OL
Output High Voltage, V
OH
Output Capacitance, C
OUT
DIGITAL INPUTS (DIN, SCLK, CS)
Input Current
Input Low Voltage, V
IL
Input High Voltage, V
IH
Pin Capacitance
DIGITAL OUTPUT (DOUT)
Output High Voltage, V
OH
Output Low Voltage, V
OL
Output Capacitance, C
OUT
POWER REQUIREMENTS
Supply Voltage
Supply Current
At 3.3 V
At 5.5 V
1 SPS Current
At 3.3 V
At 5.5 V
0.0625
0.0078
240
6
60
±0.002
±0.015
0.1
°C
°C
ms
ms
ms
°C
°C
°C/V
0.1
0.7 ×
V
DD
2
5
0.4
μA
V
V
pF
CT and INT pins pulled up to 5.5 V
I
OL
= 2 mA at 5.5 V, I
OL
= 1 mA at 3.3 V
±1
0.4
0.7 ×
V
DD
5
V
OH
−
0.3
0.4
50
2.7
210
250
46
65
5.5
265
300
10
μA
V
V
pF
V
V
pF
V
μA
μA
μA
μA
V
IN
= 0 V to V
DD
I
SOURCE
= I
SINK
= 200 μA
I
OL
= 200 μA
Peak current while converting, SPI interface inactive
Peak current while converting, SPI interface inactive
V
DD
= 3.3 V, 1 SPS mode, T
A
= 25°C
V
DD
= 5.5 V, 1 SPS mode, T
A
= 25°C
Rev. 0 | Page 3 of 24
ADT7311
Parameter
Shutdown Current
At 3.3 V
At 5.5 V
Power Dissipation Normal Mode
Power Dissipation 1 SPS
1
Data Sheet
Min
Typ
2.0
5.2
700
150
Max
15
25
Unit
μA
μA
μW
μW
Test Conditions/Comments
Supply current in shutdown mode
Supply current in shutdown mode
V
DD
= 3.3 V, normal mode at 25°C
Power dissipated for V
DD
= 3.3 V, T
A
= 25°C
Accuracy includes lifetime drift.
SPI TIMING SPECIFICATIONS
T
A
= −40°C to +150°C, V
DD
= 2.7 V to 5.5 V, unless otherwise noted. All input signals are specified with rise time (t
R
) = fall time (t
F
) = 5 ns
(10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
Table 2.
Parameter
1, 2
t
1
t
2
t
3
t
4
t
5
t
6
Limit at T
MIN
, T
MAX
0
100
100
30
25
5
60
80
10
80
0
0
60
80
10
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns min
ns min
ns max
ns max
ns min
Conditions/Comments
CS falling edge to SCLK active edge setup time
SCLK high pulse width
SCLK low pulse width
Data setup time prior to SCLK rising edge
Data hold time after SCLK rising edge
Data access time after SCLK falling edge
V
DD
= 4.5 V to 5.5 V
V
DD
= 2.7 V to 3.6 V
Bus relinquish time after CS inactive edge
SCLK inactive edge to CS rising edge hold time
CS falling edge to DOUT active time
V
DD
= 4.5 V to 5.5 V
V
DD
= 2.7 V to 3.6 V
SCLK inactive edge to DOUT low
t
73
t
8
t
9
t
10
1
2
Sample tested during initial release to ensure compliance. All input signals are specified with t
R
= t
F
= 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
See Figure 2.
3
This means that the times quoted in the timing characteristics in Table 2 are the true bus relinquish times of the part and, as such, are independent of external bus
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