EEWORLDEEWORLDEEWORLD

Part Number

Search

87917-323LF

Description
Board Stacking Connector, 23 Contact(s), 1 Row(s), Male, Straight, Solder Terminal, LEAD FREE
CategoryThe connector    The connector   
File Size297KB,4 Pages
ManufacturerAmphenol
Websitehttp://www.amphenol.com/
Environmental Compliance  
Download Datasheet Parametric View All

87917-323LF Overview

Board Stacking Connector, 23 Contact(s), 1 Row(s), Male, Straight, Solder Terminal, LEAD FREE

87917-323LF Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerAmphenol
package instructionLEAD FREE
Reach Compliance Codecompliant
Connector typeBOARD STACKING CONNECTOR
Contact to complete cooperationGOLD (50) OVER NICKEL
Contact completed and terminatedGOLD (50) OVER NICKEL
Contact point genderMALE
Contact materialPHOSPHOR BRONZE
DIN complianceNO
Filter functionNO
IEC complianceNO
JESD-609 codee4
MIL complianceNO
Manufacturer's serial number87917
Mixed contactsNO
Installation methodSTRAIGHT
Installation typeBOARD
Number of rows loaded1
OptionsGENERAL PURPOSE
Terminal pitch2.54 mm
Termination typeSOLDER
Total number of contacts23
UL Flammability Code94V-0
PDM: Rev:AC
STATUS:
Released
Printed: Jul 20, 2006
.
fpga+ dac902u problem
I'm working on an FPGA DDS function signal generator recently. I'm using a 12-bit DAC902U, but can't get it to work. Can anyone give me some advice? The schematic is attached. [img=55,49]file:///C:/Us...
绿草高原 FPGA/CPLD
How many timers does MPS430G2553 have?
I see in the documentation that 2553 has two timers, but why is there only the register definition of TIMER_A in the header file of the 430ware routine? Also, the official documentation says there are...
jishuaihu Microcontroller MCU
Has anyone used the Red Hurricane II FPGA development board? Help~
[size=5][color=red]The chip on the CY1C12 development board I have is the FPGA EP1C12Q240C8. Today I used a small program to try to light up the four seven-segment digital tubes. It uses dynamic displ...
zqzq501311 FPGA/CPLD
Windows CE6.0 USB keyboard and mouse
Hello everyone, when I am customizing the system, I want to add support for USB keyboard and mouse. May I ask which components, Reg files and BIB files I need to add?...
dragonkjl Embedded System
A few tips on XILINX FPGA design
Tips on XILINX FPGA design 1. Use a global clock buffer BUFG for the clock signal 2. Try to use only one clock edge to register data 3. Do not generate clocks internally except for the clocks generate...
cobble1 FPGA/CPLD
EE_FPGA V1.0 Debugging Progress (Updated on 2010.10.17)
front:Reverse:Current progress: 1. Minimum system operation 2. LED work 3. Key work 4. The USB to serial port driver is normal and the serial port works normallyThe pictures will be posted later, plea...
chenzhufly FPGA/CPLD

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2721  1788  2760  143  157  55  36  56  3  4 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号