VSC6424 datasheet, PDF - EEWORLD Datasheet

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VSC6424: Description500 Mb/s Video Shift Register IC; File Size209KB，18 Pages; ManufacturerVitesse Semiconductor Corporation; Websitehttp://www.vitesse.com/

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VSC6424 Overview

500 Mb/s Video Shift Register IC

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VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Datasheet

VSC6424

Features

• Multiplex or Demultiplex Operation

• Selectable Shift Register Length

• 500Mb/s Operation using internal timing

• 250Mb/s Operation using external timing

• Functional Replacement for Bt424

• External ECL Reference Voltage (-1.32 V)

500 Mb/s Video

Shift Register IC

• ECL and TTL I/Os: ECL for high-speed interface,

TTL for low-speed interface

• Power Supplies: +3.3V and -2V @ 2.7 Watts (Max.)

• Commercial (0

to +70

C) Temperature Range

• Package: 14mm x 20mm 128 PQFP

General Description

The VSC6424 is a 500Mb/s video shift register IC that is based on a 40-bit user-configured shift register.

The shift register may be used either as a multiplexer (parallel in, serial out) or as a demultiplexer (serial in, par-

allel out). The VSC6424 can be configured into 8 5-bit, 8 4-bit, 5 8-bit, 4 10-bit, 2 16-bit, 2 20-bit, 1 32-bit, or 1

40-bit shift register.

VSC6424 Functional Block Diagram

HBLANK

VBLANK

A<0:4>

AEN/RETIME

(ECL)

SIN

Input

Latch

(TTL)

DOUT<0:7>

High

Speed

Interface

(ECL)

SB<0:39>

Low

Speed

Interface

(TTL)

40-bit

DE-

MUX

Shift

CLKOUT

Timing Control

S<0:2>

MODE

INT/EXTN

OPS

LLDN

SEN/DIVC

SLDN/SYNC

DIN<0:9>

(TTL)

CLK

(ECL)

Clock

Generator

Phase

otation

CLKE

(ECL)

CLKT

(TTL)

SP<0:2>

G52236-0, Rev 3.0

7/13/99

VITESSE

SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

Page 1

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Datasheet

VSC6424

Figure 1: Synchronized VSC6424 Block Diagram

VSC6424

SLDN/SYNC

CLKT

500 Mb/s Video

Shift Register IC

120

VSC6424

SLDN/SYNC

3 - 30

VSC6424

SLDN/SYNC

Synchronization

Several VSC6424 chips can be synchronized together while in internal timing mode by connecting the slow

speed TTL clock output (CLKT) of a master chip to the synchronization input (SYNC) of a slave chip. The inter-

nal timing generator synchronizes to the rising edge of the SYNC input. Given that (n) is the number of high

speed clock cycles for a given modulus mode, synchronization takes two times (n) or (2n) clock cycles to lock

in. If it is necessary to synchronize more than two VSC6424 devices use the TTL clock output (CLKT) from

one chip to drive the SYNC inputs of each of the slave devices. See Figure 2 for a block diagram. See Figure 7

for a timing illustration of the synchronization timing of the slave chip. See Table 5 to determine (n) for a

selected modulus.

In MUX mode multiple VSC6424 chips can also be synchronized by providing a slow speed clock to the

SYNC input on all of the devices. This slow speed clock must be synchronized with high speed clock and based

on the modulus that the MUX is set to. For example if the VSC6424 is set to 8:1 mode and the high speed clock

is set to 400MHz then the SYNC input must be 50MHz.

MPU Address Interface

Address Interface

mode translates TTL compatible addresses to ECL compatible output levels. This is

provided for compatibility with the Bt424. When the Address Enable (AEN) signal is low, data from the

Address Line

A<0:4>

TTL input pins is transferred to the

DOUT<0,2,4,6,7>

ECL output pins with one clock

cycle delay. When

AEN

is high, the

A<0:4>

inputs are ignored. The

DOUT<0:7>

data is always synchronized

CLK,

regardless of the state of

AEN.

See Figure 9 for a timing illustration of this function.

Video Blanking

The VSC6424 also has a blanking function for video applications. In multiplexer mode, this function allows

zeroing of the high speed outputs (DOUT<0:7>). Setting

HBLANK

VBLANK

low drives all

DOUT<0:7>

outputs low synchronously with the clock (CLK). The outputs will be driven low on the modulus boundary. The

outputs are driven low for (n) clock cycles given that (n) is the modulus mode that the chip is set to. See table 4

to determine the value of (n) for a given modulus.

G52236-0, Rev 3.0

7/13/99

VITESSE

SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

Page 5

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