Am29LV065MU
Data Sheet
RETIRED
PRODUCT
This product has been retired and is not available for designs. For new and current designs,
S29GL064A supersedes Am29LV065MU and is the factory-recommended migration path. Please
refer to the S29GL064A datasheet for specifications and ordering information. Availability of this
document is retained for reference and historical purposes only.
The following document contains information on Spansion memory products.
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal data sheet improvement and are noted in the
document revision summary.
For More Information
Please contact your local sales office for additional information about Spansion memory solutions.
Publication Number
25262
Revision
C
Amendment
4
Issue Date
September 12, 2006
THIS PAGE LEFT INTENTIONALLY BLANK.
DATA SHEET
Am29LV065MU
64 Megabit (8 M x 8-Bit) MirrorBit™ 3.0 Volt-only
Uniform Sector Flash Memory with VersatileI/O™ Control
This product has been retired and is not available for designs. For new and current designs, S29GL064A supersedes Am29LV065MU and is the factory-recom-
mended migration path. Please refer to the S29GL064A datasheet for specifications and ordering information. Availability of this document is retained for reference
and historical purposes only.
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
Single power supply operation
— 3 volt read, erase, and program operations
VersatileI/O™ control
— Device generates and tolerates data voltages on CE#
and DQ inputs/outputs as determined by the voltage
on the V
IO
pin; operates from 1.65 to 3.6 V
Manufactured on 0.23 µm MirrorBit process
technology
SecSi™ (Secured Silicon) Sector region
— 256-byte sector for permanent, secure identification
through an 16-byte random Electronic Serial Number,
accessible through a command sequence
— May be programmed and locked at the factory or by
the customer
Flexible sector architecture
— One hundred twenty-eight 64 Kbyte sectors
Compatibility with JEDEC standards
— Provides pinout and software compatibility for
single-power supply flash, and superior inadvertent
write protection
Minimum 100,000 erase cycle guarantee per sector
20-year data retention at 125°C
PERFORMANCE CHARACTERISTICS
High performance
— 90 ns access time
— 25 ns page read times
— 0.5 s typical sector erase time
— 11 µs typical effective write buffer byte programming
time: 32-byte write buffer reduces overall
programming time for multiple-byte updates
— 8-byte read page buffer
— 32-byte write buffer
Low power consumption (typical values at 3.0 V,
5 MHz)
— 30 mA typical active read current
— 50 mA typical erase/program current
— 1 µA typical standby mode current
Package options
— 48-pin TSOP
— 63-ball FBGA
SOFTWARE & HARDWARE FEATURES
Software features
— Program Suspend & Resume: read other sectors
before programming operation is completed
— Erase Suspend & Resume: read/program other
sectors before an erase operation is completed
— Data# polling & toggle bits provide status
— Unlock Bypass Program command reduces overall
multiple-byte programming time
— CFI (Common Flash Interface) compliant: allows host
system to identify and accommodate multiple flash
devices
Hardware features
— Sector Group Protection: hardware method of
preventing write operations within a sector group
— Temporary Sector Unprotect: V
ID
-level method of
changing code in locked sectors
— ACC (high voltage) pin accelerates programming
time for higher throughput during system production
— Hardware reset pin (RESET#) resets device
— Ready/Busy# pin (RY/BY#) detects program or erase
cycle completion
This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication#
25262
Rev:
C
Amendment/4
Issue Date:
September 12, 2006
Refer to AMD’s Website (www.amd.com) for the latest information.
D A T A
S H E E T
GENERAL DESCRIPTION
The Am29LV065MU is a 64 Mbit, 3.0 volt single power
supply flash memory devices organized as 8,388,608
bytes. The device has an 8-bit wide data bus, and can
be programmed either in the host system or in stan-
dard EPROM programmers.
An access time of 90, 100, 110, or 120 ns is available.
Note that each device has a specific operating voltage
range (V
CC
) and an I/O voltage range (V
IO
), as speci-
fied in “Product Selector Guide” on page 5 and “Order-
ing Information” on page 9. The device is offered in a
48-pin TSOP or 63-ball FBGA package. Each device
has separate chip enable (CE#), write enable (WE#)
and output enable (OE#) controls.
Each device requires only a
single 3.0 volt power
supply
for both read and write functions. In addition to
a V
CC
input, a high-voltage
accelerated program
(ACC)
input provides shorter programming times
through increased current. This feature is intended to
facilitate factory throughput during system production,
but may also be used in the field if desired.
The device is entirely command set compatible with
the
JEDEC single-power-supply Flash standard.
Commands are written to the device using standard
microprocessor write timing. Write cycles also inter-
nally latch addresses and data needed for the pro-
gramming and erase operations.
The
sector erase architecture
allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Device programming and erasure are initiated through
command sequences. Once a program or erase oper-
ation has begun, the host system need only poll the
DQ7 (Data# Polling) or DQ6 (toggle)
status bits
or
monitor the
Ready/Busy# (RY/BY#)
output to deter-
mine whether the operation is complete. To facilitate
programming, an
Unlock Bypass
mode reduces com-
mand sequence overhead by requiring only two write
cycles to program data instead of four.
The
VersatileI/O™
(V
IO
) control allows the host sys-
tem to set the voltage levels that the device generates
and tolerates on the CE# control input and DQ I/Os to
the same voltage level that is asserted on the V
IO
pin.
See “Ordering Information” on page 9. for valid V
IO
op-
tions.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of sectors of memory.
This can be achieved in-system or via programming
equipment.
The
Erase Suspend/Erase Resume
feature allows
the host system to pause an erase operation in a given
sector to read or program any other sector and then
complete the erase operation. The
Program Sus-
pend/Program Resume
feature enables the host sys-
tem to pause a program operation in a given sector to
read any other sector and then complete the program
operation.
The
hardware RESET# pin
terminates any operation
in progress and resets the device, after which it is then
ready for a new operation. The RESET# pin may be
tied to the system reset circuitry. A system reset would
thus also reset the device, enabling the host system to
read boot-up firmware from the Flash memory device.
The device reduces power consumption in the
standby mode
when it detects specific voltage levels
on CE# and RESET#, or when addresses have been
stable for a specified period of time.
The
SecSi™ (Secured Silicon) Sector
provides a 256
byte area for code or data that can be permanently
protected. Once this sector is protected, no further
changes within the sector can occur.
AMD MirrorBit flash technology combines years of
Flash memory manufacturing experience to produce
the highest levels of quality, reliability and cost effec-
tiveness. The device electrically erases all bits within a
sector simultaneously via hot-hole assisted erase. The
data is programmed using hot electron injection.
2
Am29LV065MU
September 12, 2006
D A T A
S H E E T
MIRRORBIT 64 MBIT DEVICE FAMILY
Device
LV065MU
LV640MT/B
LV640MH/L
LV641MH/L
LV640MU
Bus
x8
x8/x16
x8/x16
x16
x16
Sector
Architecture
Uniform (64 Kbyte)
Boot (8 x 8 Kbyte
at top & bottom)
Uniform (64 Kbyte)
Uniform (32 Kword)
Uniform (32 Kword)
Packages
48-pin TSOP (std. & rev. pinout),
63-ball FBGA
48-pin TSOP, 63-ball Fine-pitch BGA,
64-ball Fortified BGA
56-pin TSOP (std. & rev. pinout),
64 Fortified BGA
48-pin TSOP (std. & rev. pinout)
63-ball Fine-pitch BGA,
64-ball Fortified BGA
V
IO
Yes
No
Yes
Yes
Yes
RY/BY#
Yes
Yes
Yes
No
Yes
WP#, ACC
ACC only
WP#/ACC pin
WP#/ACC pin
Separate WP#
and ACC pins
ACC only
WP# Protection
No WP#
2 x 8 Kbyte
top or bottom
1 x 64 Kbyte
high or low
1 x 32 Kword
top or bottom
No WP#
RELATED DOCUMENTS
To download related documents, click on the following
links or go to www.amd.com
→
Flash Memory
→
Prod-
uct Information
→
MirrorBit
→
Flash Information
→
Tech-
nical Documentation.
MirrorBit™ Flash Memory Write Buffer Programming
and Page Buffer Read
Implementing a Common Layout for AMD MirrorBit
and Intel StrataFlash Memory Devices
Migrating from Single-byte to Three-byte Device IDs
AMD MirrorBit™ White Paper
September 12, 2006
Am29LV065MU
3
京公网安备 11010802033920号
EEWORLD
