512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
DDR2 Registered SDRAM MODULE
240pin Registered Module based on 512Mb C-die
72-bit ECC
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure couldresult in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.2 Aug. 2005
512MB, 1GB, 2GB Registered DIMMs
DDR2 Registered DIMM Ordering Information
Part Number
M393T6553CZ3-CD5/CC
M393T6553CZA-CE7/E6/D5/CC
M393T2953CZ3-CD5/CC
M393T2953CZA-CE7/E6/D5/CC
M393T2950CZ3-CD5/CC
M393T2950CZA-CE7/E6/D5/CC
M393T5750CZ3-CD5/CC
M393T5750CZA-CE7/E6/D5/CC
Density
512MB
512MB
1GB
1GB
1GB
1GB
2GB
2GB
Organization
64Mx72
64Mx72
128Mx72
128Mx72
128Mx72
128Mx72
256Mx72
256Mx72
Component Composition
64Mx8(K4T51083QC)*9EA
64Mx8(K4T51083QC)*9EA
64Mx8(K4T51083QC)*18EA
64Mx8(K4T51083QC)*18EA
128Mx4(K4T51043QC)*18EA
128Mx4(K4T51043QC)*18EA
128Mx4(K4T51043QC)*36EA
128Mx4(K4T51043QC)*36EA
Number of Rank
1
1
2
2
1
1
2
2
DDR2 SDRAM
Parity Register
X
O
X
O
X
O
X
O
Height
30mm
30mm
30mm
30mm
30mm
30mm
30mm
30mm
Note: “Z” of Part number(11th digit) stand for Lead-free products.
Note: “3” of Part number(12th digit) stand for Dummy Pad PCB products.
Note: "A" of Part number(12th digit) stand for Parity Register products.
Features
• Performance range
E7(DDR2-800)
Speed@CL3
Speed@CL4
Speed@CL5
CL-tRCD-tRP
400
533
800
5-5-5
E6(DDR2-667)
400
533
667
5-5-5
D5(DDR2-533)
400
533
-
4-4-4
CC(DDR2-400)
400
400
-
3-3-3
Unit
Mbps
Mbps
Mbps
CK
• JEDEC standard 1.8V ± 0.1V Power Supply
• V
DDQ
= 1.8V ± 0.1V
• 200 MHz f
CK
for 400Mb/sec/pin, 267MHz f
CK
for 533Mb/sec/pin, 333MHz f
CK
for 667Mb/sec/pin, 400MHz f
CK
for 800Mb/sec/pin
• 4 Banks
• Posted CAS
• Programmable CAS Latency: 3, 4, 5
• Programmable Additive Latency: 0, 1 , 2 , 3 and 4
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination with selectable values(50/75/150 ohms or disable)
• PASR(Partial Array Self Refresh)
• Average Refresh Period 7.8us at lower than a T
CASE
85°C, 3.9us at 85°C < T
CASE
< 95
°C
-
support
High Temperature Self-Refresh rate enable feature
• Serial presence detect with EEPROM
• DDR2 SDRAM Package: 60ball FBGA - 128Mx4/64Mx8
• All of Lead-free products are compliant for RoHS
Note: For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram.
Address Configuration
Organization
128Mx4(512Mb) based Module
64Mx8(512Mb) based Module
Row Address
A0-A13
A0-A13
Column Address
A0-A9,A11
A0-A9
Bank Address
BA0-BA1
BA0-BA1
Auto Precharge
A10
A10
Rev. 1.2 Aug. 2005
512MB, 1GB, 2GB Registered DIMMs
Pin Configurations (Front side/Back side)
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
DDR2 SDRAM
Front
A4
V
DDQ
A2
V
DD
KEY
V
SS
V
SS
V
DD
NC/Par_In
V
DD
A10/AP
BA0
V
DDQ
WE
CAS
V
DDQ
S1
4
Front
V
REF
V
SS
DQ0
DQ1
V
SS
DQS0
DQS0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
DQS1
DQS1
V
SS
RESET
NC
V
SS
DQ10
DQ11
V
SS
DQ16
DQ17
V
SS
DQS2
DQS2
V
SS
DQ18
Pin
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
Back
V
SS
DQ4
DQ5
V
SS
DM0/DQS9
NC/DQS9
V
SS
DQ6
DQ7
V
SS
DQ12
DQ13
V
SS
DM1/DQS10
NC/DQS10
V
SS
RFU
RFU
V
SS
DQ14
DQ15
V
SS
DQ20
DQ21
V
SS
DM2/DQS11
NC/DQS11
V
SS
DQ22
DQ23
Pin
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Front
DQ19
V
SS
DQ24
DQ25
V
SS
DQS3
DQS3
V
SS
DQ26
DQ27
V
SS
CB0
CB1
V
SS
DQS8
DQS8
V
SS
CB2
CB3
V
SS
V
DDQ
CKE0
V
DD
NC
NC/Err_Out
V
DDQ
A11
A7
V
DD
A5
Pin
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
Back
V
SS
DQ28
DQ29
V
SS
DM3/DQS12
NC/DQS12
V
SS
DQ30
DQ31
V
SS
CB4
CB5
V
SS
DM8/DQS17
NC/DQS17
V
SS
CB6
CB7
V
SS
V
DDQ
CKE1
4
V
DD
NC
NC
V
DDQ
A12
A9
V
DD
A8
A6
Pin
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
Pin
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
Back
V
DDQ
A3
A1
V
DD
CK0
CK0
V
DD
A0
V
DD
BA1
V
DDQ
RAS
S0
V
DDQ
ODT0
A13
V
DD
V
SS
DQ36
DQ37
V
SS
DM4/DQS13
NC/DQS13
V
SS
DQ38
DQ39
V
SS
DQ44
DQ45
V
SS
Pin
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Front
V
SS
DQS5
DQS5
V
SS
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
SA2
NC(TEST)
V
SS
DQS6
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DQS7
DQS7
V
SS
DQ58
DQ59
V
SS
SDA
SCL
Pin
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Back
DM5/DQS14
NC/DQS14
V
SS
DQ46
DQ47
V
SS
DQ52
DQ53
V
SS
RFU
RFU
V
SS
DM6/DQS15
NC/DQS15
V
SS
DQ54
DQ55
V
SS
DQ60
DQ61
V
SS
DM7/DQS16
NC/DQS16
V
SS
DQ62
DQ63
V
SS
VDDSPD
SA0
SA1
ODT1
V
DDQ
V
SS
DQ32
DQ33
V
SS
DQS4
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
DQ41
NC = No Connect, RFU = Reserved for Future Use
1. RESET (Pin 18) is connected to both OE of PLL and Reset of register.
2. The Test pin (Pin 102) is reserved for bus analysis probes and is not connected on normal memory modules (DIMMs)
3. NC/Err_Out ( Pin 55) and NC/Par_In (Pin 68) are for optional function to check address and command parity.
4. CKE1,S1 Pin is used for double side Registered DIMM.
Pin Description
Pin Name
CK0
CK0
CKE0, CKE1
RAS
CAS
WE
S0, S1
A0~A9, A11~A13
A10/AP
BA0, BA1
SCL
SDA
SA0~SA2
Par_In
Err_Out
RESET
Description
Clock Inputs, positive line
Clock inputs, negative line
Clock Enables
Row Address Strobe
Column Address Strobe
Write Enable
Chip Selects
Address Inputs
Address Input/Autoprecharge
DDR2 SDRAM Bank Address
Serial Presence Detect (SPD) Clock Input
SPD Data Input/Output
SPD address
Parity bit for the Address and Control bus
Parity error found in the Address and Control bus
Register and PLL control pin
Pin Name
ODT0~ODT1
DQ0~DQ63
CB0~CB7
DQS0~DQS8
DQS0~DQS8
DM(0~8),DQS(9~17)
DQS9~DQS17
RFU
NC
TEST
V
DD
V
DDQ
V
SS
V
REF
V
DDSPD
Description
On die termination
Data Input/Output
Data check bits Input/Output
Data strobes
Data strobes, negative line
Data Masks / Data strobes (Read)
Data strobes (Read), negative line
Reserved for Future Use
No Connect
Memory bus test tool
(Not Connect and Not Useable on DIMMs)
Core Power
I/O Power
Ground
Input/Output Reference
SPD Power
*The VDD and VDDQ pins are tied to the single power-plane on PCB.
Rev. 1.2 Aug. 2005
512MB, 1GB, 2GB Registered DIMMs
Input/Output Functional Description
Symbol
CK0
CK0
CKE0~CKE1
Type
Input
Input
Input
Function
DDR2 SDRAM
Positive line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.
Negative line of the differential pair of system clock inputs that drives the input to the on-DIMM PLL.
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low
initiates the Power Down mode, or the Self Refresh mode.
Enables the associated SDRAM command decoder when low and disables decoder when high. When decoder is disabled,
new commands are ignored but previous operations continue.
These input signals also disable all outputs (except CKE and ODT) of the register(s) on the DIMM when both inputs are
high.
I/O bus impedance control signals.
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the
SDRAM.
Reference voltage for SSTL_18 inputs
Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity
Selects which SDRAM bank of four is activated.
During a Bank Activate command cycle, Address defines the row address.
During a Read or Write command cycle, Address defines the column address. In addition to the column address, AP is
used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected
and BA0, BA1 defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command
cycle, AP is used in conjunction with BA0, BA1 to control which bank(s) to precharge. If AP is high, all banks will be pre-
charged regardless of the state of BA0 or BA1. If AP is low, BA0 and BA1 are used to define which bank to precharge.
Data and Check Bit Input/Output pins
Masks write data when high, issued concurrently with input data. Both DM and DQ have a write latency of one clock once
the write command is registered into the SDRAM.
Power and ground for the DDR SDRAM input buffers and core logic
Positive line of the differential data strobe for input and output data.
Negative line of the differential data strobe for input and output data.
These signals are tied at the system planar to either V
SS
or V
DDSPD
to configure the serial SPD EEPROM address range.
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA
bus line to V
DDSPD
to act as a pullup.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time
to V
DDSPD
to act as a pullup.
Serial EEPROM positive power supply (wired to a separate power pin at the connector which supports from 1.7 Volt to 3.6
Volt operation).
The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL. When low, all register outputs
will be driven low and the PLL clocks to the DRAMs and register(s) will be set to low level (The PLL will remain synchro-
nized with the input clock )
Parity bit for the Address and Control bus. ( “1 “ : Odd, “0 “ : Even)
Parity error found in the Address and Control bus
Used by memory bus analysis tools (unused on memory DIMMs)
S0~S1
Input
ODT0~ODT1
RAS, CAS, WE
V
REF
V
DDQ
BA0~BA1
Input
Input
Supply
Supply
Input
A0~A9,A10/AP
A11~A13
Input
DQ0~63,
CB0~CB7
DM0~DM8
V
DD
, V
SS
DQS0~DQS17
DQS0~DQS17
SA0~SA2
SDA
SCL
V
DDSPD
RESET
Par_In
Err_Out
TEST
In/Out
Input
Supply
In/Out
In/Out
Input
In/Out
Input
Supply
Input
Input
Input
In/Out
Rev. 1.2 Aug. 2005
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
Functional Block Diagram: 512MB, 64Mx72 Module
(populated as 1 rank of x8 DDR2 SDRAMs)
M393T6553CZ3 / M393T6553CZA
RS0
DQS0
DQS0
DM0/DQS9
NC/DQS9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1
DQS1
DM1/DQS10
NC/DQS10
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DQS2
DM2/DQS11
NC/DQS11
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3
DQS3
DM3/DQS12
NC/DQS12
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS8
DQS8
DM8/DQS17
NC/DQS17
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DM/ NU/ CS
RDQS RDQS
DQS DQS
DM/ NU/ CS
RDQS RDQS
DQS DQS
DM/ NU/ CS
RDQS RDQS
DQS DQS
DM/ NU/ CS
RDQS RDQS
DQS DQS
DM/ NU/ CS
RDQS RDQS
DQS DQS
DQS4
DQS4
DM4/DQS13
NC/DQS13
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS5
DQS5
DM5/DQS14
NC/DQS14
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS6
DQS6
DM6/DQS15
NC/DQS15
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS7
DQS7
DM7/DQS16
NC/DQS16
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM/ NU/ CS
RDQS RDQS
DQS DQS
DM/ NU/ CS
RDQS RDQS
DQS DQS
DM/ NU/ CS
RDQS RDQS
DQS DQS
DM/ NU/ CS
RDQS RDQS
DQS DQS
D0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D4
D1
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D5
D2
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D6
D3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D7
Serial PD
SCL
WP A0
A1
A2
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
SDA
V
DDSPD
V
DD
/V
DDQ
VREF
V
SS
Serial PD
D0 - D8
D0 - D8
D0 - D8
D8
SA0 SA1 SA2
Signals for Address and Command Parity Function (M393T6553CZA)
1:1
R
E
G
I
S
T
E
R
RST
S0*
BA0-BA1
A0-A13
RAS
CAS
WE
CKE0
ODT0
RESET
PCK7
PCK7
RSO-> CS : DDR2 SDRAMs D0-D8
RBA0-RBA1 -> BA0-BA1 : DDR2 SDRAMs D0-D8
RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D8
RRAS -> RAS : DDR2 SDRAMs D0-D8
RCAS -> CAS : DDR2 SDRAMs D0-D8
RWE -> WE : DDR2 SDRAMs D0-D8
RCKE0 -> CKE : DDR2 SDRAMs D0-D8
RODT0 -> ODT0 : DDR2 SDRAMs D0-D8
* S0 connects to DCS and VDD connects to CSR on the register.
CK0
CK0
RESET
V
SS
V
SS
PAR_IN
100K ohms
C0
C1
Register
PPO
QERR
Err_Out
PAR_IN
The resistors on Par_In, A13, A14, A15, BA2 and the
signal line of Err_Out refer to the section: "Register
Options for Unused Address inputs"
Notes :
1. DQ-to-I/O wiring may be changed within a byte.
2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.
3. Unless otherwise noted, resister values are 22 Ohms
P
L
L
OE
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8
PCK7 -> CK : Register
PCK7 -> CK : Register
Rev. 1.2 Aug. 2005
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